Contact hole pattern mask, manufacturing method thereof and semiconductor device

Abstract

The invention provides a contact hole pattern mask, a manufacturing method thereof and a semiconductor device. The contact hole pattern mask is used for manufacturing a drain electrode contact hole pattern of a buried channel array transistor, and a drain electrode contact hole is a contact hole for connecting a drain electrode line of drain electrodes of two of the transistors and the drain electrode of each transistor; and the contact hole pattern mask disclosed by the invention is elliptical. An included angle between the long axis of the ellipse and the drain electrode line is smaller than or equal to 45 degrees. The method comprises the following steps of: determining an optical proximity correction model of the contact hole pattern mask according to the specification of the contact hole pattern; determining an overlay margin; and manufacturing an elliptical contact hole pattern mask according to the overlay margin. By means of the area increase caused by the long axis, the overlay margin of the long axis is enlarged, and the generated overlapping distribution is relatively stable, so that the defect of the contact hole is reduced, and the yield of manufacturing the contact hole is improved.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, in particular to a contact hole pattern mask, a manufacturing method thereof and a semiconductor device. Background technique [0002] As the pattern size of Dynamic Random Access Memory (DRAM) becomes smaller, the overlay between patterns becomes more and more important. [0003] Currently, the industry is looking for solutions to reduce overlay errors and methods to increase overlay margins. As DRAM patterns get smaller, overlay margins get smaller. For example, the pre-process and post-process of DRAM manufacturing need to be overlapped, but because of the overlay error, the contact area between the patterns becomes smaller, which leads to the deterioration of the yield of DRAM, so how to increase the overlay margin becomes relatively important. [0004] Such as figure 1 As shown, BCAT is a buried channel array transistor (buried channel array transistor, BCAT). The current ...

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Problems solved by technology

For example, the pre-process and post-process of DRAM manufacturing need to be overlapped, but because of the overlay error, the contact area between the patterns becomes smaller, which leads to the deterioration of the yield of DRAM, so how to increase the overlay margin becomes relatively important

[0004] like figure 1 As shown, BCAT is a buried channel array transistor (buried channel array transistor, BCAT). The current drain line contact (drain line contact, DLC) is circular, and its overlay margin is small. The traditional solution is By increasing the diameter of the hole, but this solution may lead to fusion between different contact holes, thereby reducing the yield of the contact hole

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