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Three-dimensional packaging structure and preparation method

A technology of three-dimensional packaging and rewiring structure, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc. It can solve the problems of low mounting efficiency of the top chip layer, heat dissipation of the top chip layer, difficulty in controlling the warpage of the plastic package, etc. problems, to achieve good heat dissipation performance, improve packaging efficiency, and correct warpage

Pending Publication Date: 2022-03-01
NAT CENT FOR ADVANCED PACKAGING +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the difficulty in controlling the warpage of the plastic package in the prior art, the heat dissipation problem of the top chip layer, and the low mounting efficiency of the top chip layer, thereby providing a wafer bonded three-dimensional packaging structure And preparation method and application

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  • Three-dimensional packaging structure and preparation method
  • Three-dimensional packaging structure and preparation method
  • Three-dimensional packaging structure and preparation method

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Embodiment Construction

[0027] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0028] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, ...

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Abstract

The invention relates to a three-dimensional packaging structure and a preparation method thereof, and the three-dimensional packaging structure comprises a plastic packaging structure which comprises a plastic packaging layer and a first chip located in the plastic packaging layer; and the second chip wafer is bonded with the plastic package structure, and the second chip wafer is electrically connected with the first chip. According to the three-dimensional packaging structure provided by the invention, the second chip wafer is integrally arranged on the plastic packaging structure, so that the warping degree of the plastic packaging structure can be corrected; the second chip wafer is not covered by the plastic packaging layer, so that the second chip wafer has good heat dissipation performance; and the second chip wafer is integrally bonded, so that the packaging efficiency of the chip can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-bonded three-dimensional packaging structure, a preparation method and an application. Background technique [0002] With the increasing multi-functionalization and miniaturization of electronic devices, the continuous reduction of the feature size of integrated circuits, and the continuous improvement of interconnection density, the requirements for the size of packaging and finishing are becoming more and more stringent. How to integrate multiple different sizes The high integration of various types of chips in a package is a major trend in the miniaturization trend in the field of chip packaging today. Three-dimensional stack packaging is a very effective technical way to meet the above requirements. [0003] The currently widely used three-dimensional fan-out package is to rewire the basic chip layer that has been plastic-packed together, then set the...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L25/18H01L23/31H01L23/367H01L21/50H01L21/56H01L21/60
CPCH01L25/0657H01L25/18H01L23/3107H01L23/367H01L21/50H01L21/56H01L24/80H01L2224/80
Inventor 张春艳孙鹏
Owner NAT CENT FOR ADVANCED PACKAGING