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Market low-delay interface device based on FPGA (Field Programmable Gate Array)

An interface device and low-latency technology, which is applied in the field of low-latency interface devices, can solve problems such as huge system overhead, and achieve the effects of reducing delay, reducing the number, and speeding up data output

Pending Publication Date: 2022-03-04
上海金融期货信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The current mainstream securities market processing and distribution system generally uses traditional network cards for data reception and distribution, and network cards rely on CPU to process TCP / IP data streams through software, which brings huge overhead to the system

Method used

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  • Market low-delay interface device based on FPGA (Field Programmable Gate Array)
  • Market low-delay interface device based on FPGA (Field Programmable Gate Array)
  • Market low-delay interface device based on FPGA (Field Programmable Gate Array)

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Experimental program
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Embodiment Construction

[0044] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Note that the aspects described below in conjunction with the drawings and specific embodiments are only exemplary, and should not be construed as limiting the protection scope of the present invention.

[0045] figure 1 The principle of an embodiment of the FPGA-based market low-latency interface device of the present invention is shown. See figure 1 , the device in this embodiment includes: a network receiving module and a network sending module, a quotation business module, and a system control module.

[0046] The network receiving module receives the input from the external network, and transmits the received data to the quotation business module after processing.

[0047] The network sending module receives the output of the quotation business module, and transmits the received data to the external network after processing.

[0048] T...

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PUM

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Abstract

The invention discloses a market condition low-delay interface device based on an FPGA (Field Programmable Gate Array), which is used for reducing the interface delay and greatly improving the efficiency. According to the technical scheme, an interface device uses an FPGA to achieve a PHY protocol (including a PCS layer, namely a physical coding sub-layer and an MAC layer, namely a medium access control layer) and a TCP protocol (mainly TCP mirror image processing) to receive the stock quotation, then the analyzed stock quotation is forwarded to a client through a UDP protocol, and the FPGA is used to achieve 10-gigabit Ethernet and the TCP protocol to achieve data receiving and forwarding of the stock quotation. Specifically, in the interface device provided by the invention, the original standard Ethernet layering (PCS layer and MAC layer) is improved to be realized by mixing the two layers together as a module instead of layering according to a standard protocol, so that the number of the realized modules is reduced, the time delay caused by each module is reduced, and the data output of the Ethernet interface is accelerated.

Description

technical field [0001] The invention relates to a low-delay interface device, in particular to a low-delay interface device applied to market data of financial business, especially securities business. Background technique [0002] The current mainstream securities market processing and distribution system generally uses traditional network cards for data reception and distribution, and network cards rely on CPU to process TCP / IP data streams through software, which brings huge overhead to the system. [0003] However, with the development of embedded technology, especially FPGA has the characteristics of low latency and high concurrency, how to use this characteristic of FPGA hardware in the stock market processing and distribution system to replace the traditional network card relying on CPU to process TCP / The method of IP data flow, thereby reducing the delay of market data transmission, and improving it is an urgent problem to be solved in the industry. [0004] Accord...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/02H04L69/16
CPCH04L12/02H04L69/16Y02D30/50
Inventor 陈建武陈吉芳朱恺李思昌张海荣曹俊岭王康贵
Owner 上海金融期货信息技术有限公司
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