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Semiconductor device and method of manufacturing the same
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A technology of semiconductors and laminates, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as damage to semiconductor components or wiring
Pending Publication Date: 2022-03-08
KIOXIA CORP
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Abstract
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Problems solved by technology
[0005] However, mechanical stress during wire bonding may damage semiconductor elements or wiring, etc.
Method used
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no. 1 Embodiment approach
[0025] figure 1 It is a sectional view showing an example of the structure of a semiconductor device. figure 1 The semiconductor device is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together. The array chip 1 is an example of a first chip, and the circuit chip 2 is an example of a second chip.
[0026] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11 , and an interlayer insulating film 13 under the memory cell array 11 . The insulating film 12 is, for example, a siliconoxide film or a siliconnitride film. The interlayer insulating film 13 is, for example, a siliconoxide film or a laminated film including a silicon oxide film and other insulating films.
[0027] The circuit chip 2 is disposed under the array chip 1 . Symbol S represents the bonding surface of the array chip 1 and the circuit chip 2 . The bonding surface S is an example of the...
no. 2 Embodiment approach
[0083] Figure 16 It is a sectional view showing the structure of the semiconductor device of the second embodiment. The second embodiment is different from the first embodiment in that the structure 18 is arranged in contact with the plug hole 45 .
[0084] with the first embodiment Figure 5 compared to Figure 16 In the example shown, the structures 18 are continuously provided across the area A1. In addition, the plug hole 45 is provided so as to penetrate through the structure body 18 .
[0085] Figure 17 It is a plan view showing the arrangement of the structures 18 and the plug holes 45 in the second embodiment.
[0086] Such as Figure 17 As shown, the laminated body 181 is provided so as to be in contact with the plug hole 45 . Since the insulating layers 181 a and 182 b are insulators, even if they are in contact with the vias 45 , no short circuit will occur between the vias 45 . Therefore, the operation of the control circuit including the transistor 31 is...
no. 3 Embodiment approach
[0090] Figure 18 It is a sectional view showing the structure of the semiconductor device of the third embodiment. The third embodiment is different from the first embodiment in that the laminated body of the structure 18 does not include a metal layer.
[0091] The structure 18 has a laminated body 182 that is alternately laminated so as to correspond to the laminated body 111 and includes a plurality of metallayers 182 a and a plurality of insulating layers 182 b electrically cut from the plug holes 45 . This is because, in the step of forming the memory cell array 11 , the structure 18 (layered body 182 ) is formed substantially simultaneously with the memory cell array 11 . Therefore, the position and thickness of the metal layer 182a from the surface F1 are substantially the same as those of the word line WL. In addition, the position and thickness of the insulating layer 182 b from the surface F1 are substantially the same as those of the insulating layer 51 .
[00...
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Abstract
The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes: a first chip provided with a memory cell array; and a second chip bonded to the first chip and provided with a control circuit for controlling the memory cell array. The first chip includes a substrate, a pad, a first structure, and a second structure. The substrate is disposed on the opposite side of the bonding surface of the second chip, and includes: a first surface having a memory cell array provided between the first surface and the opposing bonding surface; a second surface on the opposite side to the first surface; and an opening extending from the second surface to the first surface in the first region. The welding pad is arranged in the opening part. The first structure is provided between the first surface and the bonding surface, and is electrically connected to the pad. The second structure is provided between the first surface and the bonding surface in the first region.
Description
[0001] related application [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-150749 (filing date: September 8, 2020). This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same. Background technique [0004] In recent years, hybrid bonding technology of bonding two wafers on which semiconductor elements are formed has been introduced into CMOS (Complementary MetalOxideSemiconductor) image sensors or nonvolatile semiconductor memories. In this case, the electrode pads for wire bonding for external connection are formed so as to be exposed on the uppermost surface of the chip after thinning the substrate, for example. [0005] However, mechanical stress during wire bonding may damage semiconductor elements, wiring, and th...
Claims
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Application Information
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