Test calibration method of integrated circuit

Abstract

The invention discloses a test calibration method for an integrated circuit, which comprises the following steps of: 1) firstly, obtaining the actual clock frequency of the integrated circuit to be tested; 2) according to the actual clock frequency, the test equipment sends a command to a specified pin of the integrated circuit to be tested; 3) receiving a command through a shift register; 4) analyzing the received command, and performing testing or parameter configuration on a corresponding function module in the integrated circuit to be tested; (5) the to-be-tested integrated circuit sends the command execution condition back to the test equipment, the test equipment analyzes the received data, if the data are complete, receiving is completed, and if the to-be-tested integrated circuit needs to be continuously tested or subjected to parameter configuration, the to-be-tested integrated circuit is reset, and the step (2) is executed; and 6) if the test and parameter configuration are both completed, the test equipment sends a command for locking the integrated circuit to be tested to the integrated circuit to be tested, and the integrated circuit to be tested executes locking operation. The test calibration method can be widely applied to the design of various integrated circuits.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for testing and calibrating integrated circuits. Background technique [0002] At present, in the traditional integrated circuit test and calibration method, the test equipment and the integrated circuit under test usually use a single-wire protocol for communication, the most common is the 1-wire protocol launched by Dallas Semiconductor, such as figure 1 As shown, the protocol uses a single signal wire to transmit the clock along with the data. For this reason, it is necessary to send "0" and "1" levels on a single line, and to send a clock synchronization signal according to the transmission rate. In this way, a relatively complex encoding and synchronization scheme is required. Inside the "0" and "1" signals, a specific code pattern is constructed so that the receiving end can extract clock synchronization information from it. The disadvantage of this single-wire...

AI Technical Summary

Problems solved by technology

The disadvantage of this single-wire protocol is: the clock frequency of the sending end and the receiving end must be consistent, so as to ensure that the write time slot remains 15us or 60us, so that the timing results of the sending end and the receiving end are consistent, and the data is received correctly.

It is very difficult to ensure that the clocks of the transmitting end and the receiving end are consistent, and usually need to use a high-precision crystal oscillator or a clock recovery circuit to achieve high complexity and cost.

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