Memory controller and chip product

Abstract

The embodiment of the invention provides a memory controller and a chip product, and the memory controller comprises an asynchronous FIFO module which is configured to synchronize data or commands from a first clock domain and a second clock domain, the first clock domain is a clock domain limited by the clock frequency of the memory controller, and the second clock domain is a clock domain limited by the clock frequency of the memory controller. The second clock domain is a clock domain limited by the clock frequency of the memory; the processing unit is configured to obtain a sending interval delay value between any two adjacent commands according to the measurement delay value and a protocol delay value between any two adjacent commands specified by a memory protocol, the measurement delay value is determined by measuring the interval time variation of two adjacent commands or two adjacent beats of data transmitted from the memory control module to the memory physical interface. Through some embodiments of the invention, the delay of the memory controller from command transmission to data transmission completion is effectively reduced.

Description

technical field [0001] The present application relates to the field of memory controllers, and specifically, the embodiments of the present application relate to a memory controller and a chip product. Background technique [0002] Currently, a Soc system (that is, a system-on-a-chip) includes: a memory (for example, Dram), a memory controller (for example, a Dram controller), and a memory physical interface (for example, Dram Phy). The memory controller Dram controller is responsible for the scheduling of read and write instructions and the timing control of Dram, and the Dram phy is responsible for encoding the scheduled instructions according to the requirements of Dram, sending the corresponding write data to the memory Dram, and accepting the read from the memory Dram. fetched memory data. [0003] In the related art, the memory physical interface (for example, Dram phy) and the memory (for example, Dram) are designed according to the synchronous clock, that is, the di...

AI Technical Summary

Problems solved by technology

In the related art, for accurate timing, the main logic (including the timer) of the memory controller (for example, Dram controller) and the physical interface of the memory (for example, Dram phy) are synchronous clock designs, which leads to scheduling commands and The delay in transmitting data increases a lot

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