32 results about "Interval delay" patented technology

A method for channel sounding by an access point includes transmitting a sounding frame to a plurality of mobile stations (STAs). The sounding frame includes training symbols to be measured by each of the plurality of STAs. A sounding response frame is received from each of the plurality of STAs. The sounding response frame received from a first STA of the plurality of STAs is received at a short interframe spacing interval delay after completion of the sounding request frame transmission.

The patterns of contraction and relaxation of the heart before and during left ventricular or biventricular pacing are analyzed and displayed in real time mode to assist physicians to screen patients for cardiac resynchronization therapy, to set the optimal A-V or right ventricle to left ventricle interval delay, and to select the site(s) of pacing that result in optimal cardiac performance. The system includes an accelerometer sensor; a programmable pace maker, a computer data analysis module, and may also include a 2D and 3D visual graphic display of analytic results, i.e. a Ventricular Contraction Map. A feedback network provides direction for optimal pacing leads placement. The method includes selecting a location to place the leads of a cardiac pacing device, collecting seismocardiographic (SCG) data corresponding to heart motion during paced beats of a patient's heart, determining hemodynamic and electrophysiological parameters based on the SCG data, repeating the preceding steps for another lead placement location, and selecting a lead placement location that provides the best cardiac performance by comparing the calculated hemodynamic and electrophysiological parameters for each different lead placement location.

The invention relates to an automatic feeding device during crystal material processing, relating to auxiliary devices of crystal processing. A crystal bar storage mechanism for material preparation in early stage is arranged on one side of a distribution feeding mechanism for interval delay, a plurality of mutually relative hook teeth (22) are arranged at outer edges of at least two crystal bar conveying wheels (17), a ratchet wheel (15) arranged on a shaft is connected with a control system of the distribution feeding mechanism, and the control system of the distribution feeding mechanism drives the ratchet wheel to make the hook teeth on the crystal bar conveying wheels drive crystal bars of the crystal bar storage mechanism for the material preparation in early stage to move onto a crystal bar discharge plate (2) for guiding materials on the other side of the distribution feeding mechanism. According to the automatic feeding device disclosed by the invention, silicon cores are conveyed to the distribution feeding mechanism for the interval delay by the crystal bar storage mechanism for the material preparation in the early stage, and the distribution feeding mechanism for the interval delay realizes the interval delay conveyance of the crystal bars onto the crystal bar discharge plate for guiding the materials by the control system of the distribution feeding mechanism, thus the defect that labors need to keep an eye on the production field for a long term in the traditional processing method is prevented.

The invention discloses a high-voltage repetition-frequency impulse source based on a GL1551G type hydrogen thyratron. The high-voltage repetition-frequency impulse source based on the GL1551G type hydrogen thyratron is composed of a direct-current power supply, an energy storage system, an impulse power switch and a load. A capacitance energy storage mode is adopted in the energy storage system, a closing switch is needed by the high-voltage impulse source with the capacitance energy storage, the bigrid hydrogen thyratron is a gas switch belongs to closing switches, and the load needs to be noninductive. Through the mode of using an FPGA for achieving multi-impulse source equal interval delayed output, the effect that the high repetition frequency of the high-voltage impulse is tunable can be ensured; through a designed hydrogen thyratron grid trigger circuit, the hydrogen thyratron can be triggered to be connected reliably while the inductance value in a main circuit is reduced, and fast-rise leading edges available in the high-voltage impulse source and elimination of output impulse oscillation can be ensured.

The invention relates to a directional seismic data processing method based on Nth root stacking. The directional seismic data processing method includes that Nth root solving is performed on a group of adjacent seismic records sequentially; the seismic records after being processed are subjected to equal interval delay processing; the seismic records after time delay processing are related, and in order to inhibit signal distortion outside a main wave beam direction, Nth power processing is performed on the seismic records to acquire needed directional seismic records. Experiments show that under high-noise environment, existing seismic wave processing methods can enhance effective signals in the main wave beam direction while signal ambiguity or signal same-phase axis forking outside the main wave beam direction occurs, so that seismic data signal-to-noise ratio and resolution ratio are lowered, and subsequent seismic data processing and explaining are adversely affected. Compared with existing directional seismic wave processing methods, the directional seismic data processing method has the advantages that effective signals in original records are fully protected and enhanced, signal-to-noise ratio in the main wave beam direction is increased by n times, and more importantly, signal distortion outside the main wave beam direction is inhibited effectively.

A modulation-demodulation method for constellation split difference empty time of quick decline channels includes methods of modulation and demodulation of constellation split difference empty time. The modulation method includes: acquiring original difference empty time constellation matrix to be divided into several sub-matrixes in terms of time shaft to be carried out in equal time interval delay in light of the data frame length to be emitted to corresponding antennas. The demodulation method includes: adopting coherent time delay to the data received in terms of time sequence to be merged to ensure the merged matrix is the equivalent received matrix of the original, finally to carry out difference empty time demodulation.

The invention provides a method for improving the imaging stability of a diasonograph 4D mechanical probe. The method comprises the steps of obtaining corresponding incomplete faultage image scanningduration in the process that a probe is rotated from the first position to the second position; obtaining transmission interval delay of a driving device for driving an energy converter to move in theprocess that the energy converter is rotated from the first position to the second position; in the process that the energy converter is rotated from the first position to the second position, afterthe energy converter driving device sends out an enabled signal for enabling the energy converter to start to move, after the first delay, starting to record and scan faultage image data through an imaging system till the energy converter is moved to the second position, wherein the first delay is introduced by the compensation transmission interval. The problem that three-dimensional images are twisted along with swinging of the energy converter due to the scanning time sequence and the transmission interval of a 4D mechanical scanning probe is solved.

The invention provides a novel work application mode for an internal combustion engine. In each work application stroke, two-cylinder or multi-cylinder pistons are combined for implementing the synchronous work application. The technology is mainly used for the internal combustion engine model with more than four cylinders, and aims at achieving the goal of enabling a crank shaft to form the greater torque via the reasonable centralized utilization of piston driving force so that stronger output motive power is generated. A novel work application mode has the effects that the crank shafts in the same models generate twice torque and rotating acceleration, and the motive power of the engine can be improved by about 50 percent except the adverse factors such as work application time reduction and work application interval delay. The novel work application mode also has the beneficial effects that the conflict between the torque and the rotating speed is neutralized, so the large-torque engine realizes high speed, and large-size engines with super power can be designed; in environment-protection and energy-saving aspects, after the motive power demand is surplus, the fuel can be reduced through lowering the power, and the fuel saving effect is bout 30 percent.

The invention provides a lock capable of being quickly opened. The lock comprises a double-blade thumbing wheel, a latch bolt, a latch bolt transmission mechanism, a deadbolt, a deadbolt transmissionmechanism and a lock shell. The double-blade thumbing wheel is rotationally connected into the lock shell. A first protruding thumbing bolt and a second protruding thumbing bolt are arranged on the outer edge of the double-blade thumbing wheel. The first thumbing bolt is suitable for rotating and thumbing the deadbolt transmission mechanism. The deadbolt transmission mechanism is in transmission connection with the deadbolt. The deadbolt transmission mechanism is used for converting the rotating movement of the first thumbing bolt into the linear movement of the deadbolt. The second thumbing bolt is suitable for rotating and thumbing the latch bolt transmission mechanism. The latch bolt transmission mechanism is in transmission connection with the latch bolt. The latch bolt transmission mechanism is used for converting the rotating movement of the second thumbing bolt into the linear movement of the latch bolt. When the first thumbing bolt is disengaged from the latch bolt transmissionmechanism, the second thumbing bolt starts to abut against the latch bolt transmission mechanism. The double-blade thumbing wheel does not need to do transition movement between driving the latch bolt and driving the deadbolt, that is, no interval-delay operation exists when the twice-locked lock is opened, and unlocking time is saved.

The embodiment of the invention provides a memory controller and a chip product, and the memory controller comprises an asynchronous FIFO module which is configured to synchronize data or commands from a first clock domain and a second clock domain, the first clock domain is a clock domain limited by the clock frequency of the memory controller, and the second clock domain is a clock domain limited by the clock frequency of the memory controller. The second clock domain is a clock domain limited by the clock frequency of the memory; the processing unit is configured to obtain a sending interval delay value between any two adjacent commands according to the measurement delay value and a protocol delay value between any two adjacent commands specified by a memory protocol, the measurement delay value is determined by measuring the interval time variation of two adjacent commands or two adjacent beats of data transmitted from the memory control module to the memory physical interface. Through some embodiments of the invention, the delay of the memory controller from command transmission to data transmission completion is effectively reduced.

The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into the integrated chip. In view of the present invention, the problems that an existing clock delay adjusting circuit is low in adjustment accuracy and can not meet the requirement for high-precision time-share sampling are well solved.

A method for backup comparison table of solid state hard disk includes carry out dynamic maintenance on logical physical comparison table in volatile buffer memory of solid state hard disk; Dividing alogical physical comparison table backup into a plurality of unit backup data of a preset data amount; Backing up data in units separated by a preset interval delay time; At that same time, the flashmemory array for access user data and write unit backup data to the solid state disk is processed. However, only user data can be accessed during the delay time interval to improve the access efficiency of user data.

The invention discloses an overload hiccup protection circuit for a half-bridge topology switching power supply, which comprises an overload hiccup protection circuit and a power supply circuit. The overload hiccup protection circuit includes a driving circuit and a control circuit, the driving circuit comprises a field effect transistor Q5, thyristor SCR2, Diode D13, Resistance R58, Resistance R76, Capacitor C18, Hiccup interval delay control circuit, the capacitor C18 and the resistor R76 are connected in parallel between the cathode and the control electrode of the thyristor SCR2, the control electrode of the thyristor SCR2 is connected to the drain of the field effect transistor Q5, The cathode is connected to the source of the field effect transistor Q5, the anode of the thyristor SCR2 is connected to the cathode of the diode D13, the anode of the diode D13 is connected to the center end of the transformer T coil of the switching power supply circuit, and the source of the field effect transistor Q5 is connected to a hiccup interval delay control circuit for controlling the on-off of the field effect transistor Q5. The invention has the advantages that when the switching powersupply is overloaded, the switching power supply enters the intermittent protection mode, and after the overload phenomenon disappears, the switching power supply automatically resumes normal operation.

The invention discloses an automatic error correction method for a resistive touch screen. The automatic error correction method for the resistive touch screen comprises the steps of reading parameter data of the product model, judging whether a reference file corresponding to the product model exists or not; if the reference file does not exist, automatically generating the reference file which provides reference for follow-up correction; if the reference file exists, obtaining an upper left coordinate clicked by a user, and calculating a difference between the upper left coordinate and an upper left coordinate in the reference file; judging whether the absolute value of the difference exceeds a preset range or not, if not, accomplishing correction of the upper left coordinate, and accomplishing correction of an upper right coordinate, a lower right coordinate, a lower left coordinate and a central point coordinate in sequence in the same mode. According to the automatic error correction method for the resistive touch screen, correction misoperation can be avoided, the phenomenon that suspended halt of the resistive touch screen is caused due to misoperation of a user can be effectively avoided, and efficiency of the correction program is improved; meanwhile, after the user clicks the resistive touch screen, sampling interval delay is triggered, and misoperation such as continuous clicks can be effectively prevented.

The invention discloses a CMOS driver applied to output signal slew rate control, comprising: a delay phase locked loop DLL, a sampling circuit DFFs and a driving circuit driver which are sequentiallyconnected, wherein the delay phase locked loop comprises a phase frequency detector PFD, a charge pump circuit CP, a loop low pass filter LPF and a voltage controlled delay circuit VCDL which are sequentially connected. Compared with the typical output signal slew rate control output driver, the slew rate control provided by the invention uses an equal delay signal of the delay phase locked loop.Under the influence of PVT change, when the delay phase locked loop is locked, the phase signal clock of the delay lock phase loop maintains a constant equal interval delay, and a constant delay signal is used for superimposing to obtain a constant slew rate signal, thereby improving the defect that a large change is generated in the output signal slew rate caused by a large impact brought by thedriving capability of the conventional three-state gate slew rate control output driver due to process variations, changes in operating environment temperature, and changes in supply voltage.

The invention discloses a response method of an Internet of Things data packet in an intelligent building. The method comprises the following steps: calculating the delay amount delta W1 of each destination TP address, wherein delta W1 is equal to tint * W1/Min (W1); wherein Min (W1) refers to selecting the minimum value of all W1; calculating the correction arrival time t '= t + delta t of each data packet; wherein t is the actual time when the data packet reaches the access gateway; and sending the data packets to the Internet of Things terminal in sequence according to the sequence of the corrected arrival time. According to the load condition of gateway equipment, different processing strategies are provided for the response data packet, when the load is large, targeted flow control can be performed on different destination IPs, and the flow control considers the requirements of the frequency and the service type of the response data packet for the data packet processing timeliness, so that the data packet processing efficiency is improved. The interval delay degree calculated by the delay control algorithm is at the same number level as the average time interval, and the tolerance of the terminal to the response message delay can be reflected.

The invention discloses an automatic time delay deviation estimation and compensation device for a measurement and control antenna array, and the device carries out the preprocessing of down-conversion, filtering, integral cleaning and the like on a multi-antenna receiving signal, carries out the FFT of the preprocessed signal, builds a delay difference compensation model through the fitting of a frequency domain cross-spectrum signal, extracts the time delay deviation between multiple antennas, and compensates the integer sampling interval delay deviation and the decimal sampling interval delay deviation in the time domain and the frequency domain respectively. The method is suitable for time delay deviation alignment among signals received by multiple antennas under the condition of low signal-to-noise ratio, and has the advantages of high time delay deviation estimation and compensation precision and the like.