Digital verification method and system of Nand flash memory

Abstract

The invention discloses a digital verification method of a Nand flash memory, which comprises the following steps of: a, detecting data information on a bus of the Nand flash memory, and calculating and recording the length and the position of the data; b, randomly generating different data error positions, and recording and sequencing the error positions; c, error making is carried out on data in the Nand flash memory according to the recorded error position; and d, marking the position of the error-made data. Meanwhile, the invention also discloses a digital verification system of the Nand flash memory. By means of the scheme, on the premise that an original verification environment and a test case are not affected, data errors occurring when the flash memory works actually can be truly reflected, the credibility of verification is effectively improved, and the portability and flexibility of verification are improved.

Description

technical field [0001] The invention relates to the field of digital verification, in particular to a digital verification system and method of a Nand flash memory. Background technique [0002] With the development of technology and changes in market demand, flash memory, especially nand flash memory, has more application forms and usage requirements. Since the nand flash memory will inevitably have several bit errors even in the normal reading and writing with no problems in the operation timing and circuit stability during actual operation, so the flash memory controller often has related error detection and The correction mechanism (commonly called Error Checking and Correction, ecc for short) uses Hamming code or bch algorithm to ensure the correctness of data. At the same time, because the soc chip storage often has RAM and ROM, according to the function of the chip, they and the cpu will also perform various operations and interactions on the data of the flash memory...

AI Technical Summary

Problems solved by technology

Although this approach is intuitive and simple, it has extremely low flexibility and cannot meet the complex requirements of actual verification work. It needs test cases to cooperate with it. When the project is migrated, it needs to re-check and write test cases, and the portability is extremely poor.

More importantly, because a large number of force operations are used on the data bus, it cannot be guaranteed that the result is only the data error expected by the verification engineer without affecting other parts, which greatly reduces the reliability of the verification result and the verification risk. sharply increased

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