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Semiconductor packaging structure

A packaging structure and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of insufficient die-sticking accuracy, peeling, and inability to use high-end packaging, to avoid adhesion Insufficient sex, strength-enhancing effect

Pending Publication Date: 2022-03-29
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As a result, traditional technology (eg, substrate) process capabilities cannot meet the above-mentioned functional and size reduction requirements
Thinning is also one of the most effective ways to shrink products, taking into account the tiny wires and the resulting warpage problem. The traditional manufacturing method uses the support body design to overcome the warpage problem, but it has to face the heterogeneity (such as glass and Dielectric materials) problems such as peeling caused by the bonding surface; at the same time, it must be processed through a thinning (eg, grinding) process; moreover, the die bonding accuracy (>2um) provided by the substrate technology is insufficient, Cannot be used for high-level packaging, these problems are quite challenging at present

Method used

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  • Semiconductor packaging structure
  • Semiconductor packaging structure
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Embodiment Construction

[0031] In order to better understand the spirit of the embodiments of the present application, it will be further described below in conjunction with some preferred embodiments of the present application.

[0032] Embodiments of the present application will be described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative, diagrammatic and are used to provide a basic understanding of the application. The examples of the present application should not be construed as limiting the present application.

[0033] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances in whi...

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Abstract

The invention provides a semiconductor packaging structure. The semiconductor packaging structure comprises a first dielectric layer; a bonding pad having a protruding portion protruding from the first dielectric layer; the convex part is embedded into the solder bump; and a first barrier layer sandwiched between the bonding pad and the first dielectric layer, in which there is a gap between the first barrier layer and the solder bump, and the bonding pad and the first dielectric layer are separated by the gap. On the other hand, the invention provides a method for forming the semiconductor packaging structure so as to at least enhance the strength of the semiconductor packaging structure.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a semiconductor packaging structure. Background technique [0002] The demand for functionality and size reduction of electronic products continues to increase, and the reduction of products also forces the wire size to be continuously reduced in a limited area (such as line width / spacing below 2um / 2um), especially for high-end packages-such as 2.5 Dimensional (2.5D) / 3 Dimensional (3DIC) - Product. As a result, the process capabilities of conventional technologies (eg, substrates) cannot meet the above-mentioned requirements for functionality and size reduction. Thinning is also one of the most effective ways to shrink products, taking into account the tiny wires and the resulting warpage problem. The traditional manufacturing method uses the support body design to overcome the warpage problem, but it has to face the heterogeneity (such as glass and Dielectric materials) p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/49H01L21/60
CPCH01L23/3128H01L23/49816H01L23/49838H01L24/07H01L2224/83385H01L2224/73204H01L2224/16225H01L2224/32225H01L2924/181H01L2924/18161H01L2924/00012H01L2924/00
Inventor 吕文隆
Owner ADVANCED SEMICON ENG INC
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