High-speed data processing system and high-speed data processing method

Abstract

The invention relates to the technical field of data acquisition and processing, and aims to provide a high-speed data processing system and a high-speed data processing method. The high-speed data processing system comprises a high-speed interface, a DDR control unit, a file system protocol layer and a transmission protocol layer which are connected in sequence, the high-speed interface is used for receiving high-speed data and inputting the high-speed data into the DDR control unit, and the DDR control unit is used for caching the high-speed data into a DDR memory after receiving the high-speed data. The DDR control unit is further used for storing the high-speed data cached in the DDR memory to the solid state disk through the file system protocol layer and the transmission protocol layer in sequence, and the file system protocol layer is connected with a network port and used for achieving communication between the solid state disk and a user terminal. According to the method, a user can conveniently and intuitively check the high-speed data in the solid state disk, the visual management of the high-speed data can be realized, and meanwhile, the data processing efficiency is high and the portability is strong.

Description

technical field [0001] The invention relates to the technical field of data collection and processing, in particular to a high-speed data processing system and a high-speed data processing method. Background technique [0002] In aerospace, military industry, astronomy and other fields, high-bandwidth, high-speed data acquisition, storage and processing applications are very common. FPGA (Field Programmable Gate Array, Field Programmable Gate Array) can be used for high-speed processing and storage of raw data. At present, the acquisition of high-speed data basically needs FPGA to realize. [0003] In the prior art, high-speed data, such as radar analog signals, high-definition video signals, etc., can first be input to an FPGA-based DDR (Double Data Rate, double data rate) control unit through a high-speed interface and a high-speed protocol, and the DDR control unit can analyze high-speed data Transmission protocol to preprocess high-speed data, and then cache the preproc...

AI Technical Summary

Problems solved by technology

However, the hard disk storage speed of this solution will be greatly limited by the software performance of the host computer, and it is difficult to realize real-time storage of high-speed data; moreover, this type of processing system needs to be equipped with a server or personal computer with a PCIe interface, resulting in high-speed data storage. Poor portability of the processing system

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