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Semiconductor structure and preparation method thereof

A semiconductor and interconnect technology, applied in the field of semiconductor structure and its preparation, can solve the problem of low device integration

Pending Publication Date: 2022-04-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For this reason, the application proposes a semiconductor structure and its preparation method to solve the problem of low device integration

Method used

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0021] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The N layers of metal interconnection lines are arranged at intervals, and N is a positive integer larger than or equal to 3; the N layers of metal interconnection lines at least comprise a first interconnection line, a second interconnection line and a third interconnection line; the first interconnection line and the third interconnection line are connected through a via hole contact element, and the via hole contact element penetrates through the second interconnection line. According to the manufacturing method of the semiconductor device, the through hole is formed to penetrate through the multiple layers of metal interconnection lines, so that a specific layer of metal interconnection lines on the lower portion can be connected, the process is simplified, in addition, unnecessary metal interconnection line forming areas and unnecessary occupied space of the through hole are reduced, the poor process is improved, the integration degree of the device is improved, and the size of the device is greatly reduced.

Description

technical field [0001] The present application relates to the field of semiconductor technology, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] In semiconductor manufacturing, patterning is a very important task. In order to form finer patterns, photolithography and etching are required to make basic patterns, and multi-layer film deposition and removal are required during the process. Patterning is also the main process for forming via holes for multilayer metal interconnection. At present, the interconnection of multilayer metal interconnection lines 11' (Metalline) mostly uses via hole 12' (Via hole) interconnection, such as figure 1 As shown, in this way, the patterning process of the through hole is directly complicated, and the formed multilayer metal interconnection structure is relatively complicated, and the structure integration degree is low, which cannot meet the requirements of the continuous reduction ...

Claims

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Application Information

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IPC IPC(8): H01L23/522H01L23/528H01L21/768
Inventor 申靖浩高建峰李俊杰周娜刘卫兵
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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