Instruction processing method and device, microcontroller and readable storage medium

A technology of instruction processing and instruction caching, which is applied in the field of data processing, can solve problems such as not enough to complete two instruction fetch operations, the instruction fetch timing will not be very generous, and the system performance is small, so as to reduce impact, improve efficiency, and improve The effect of accuracy

Active Publication Date: 2022-05-24
深圳市航顺芯片技术研发有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] During the process of conceiving and implementing the present application, the inventors of the present application have found at least the following problems: the existing technology stops prefetching when encountering branch instructions, resulting in a small improvement in system performance in complex software; in addition, although the existing There are ways to predict conditional branch instructions, but in the CORTEX-M series processors, the instruction fetch timing will not be very generous

Method used

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  • Instruction processing method and device, microcontroller and readable storage medium
  • Instruction processing method and device, microcontroller and readable storage medium
  • Instruction processing method and device, microcontroller and readable storage medium

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Embodiment Construction

[0062] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

[0063] It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without furt...

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Abstract

The invention relates to the technical field of data processing, and provides an instruction processing method and device, a microcontroller and a medium, and the method comprises the steps: parsing an instruction read from a memory; after the instruction is analyzed to be a branch instruction, the types of the instruction are classified, and the offset of the instruction is calculated; calculating a next prefetch address according to the type of the instruction and the offset of the instruction; and writing the instruction into the corresponding cache region according to the type of the instruction and the next prefetch address of the instruction, and then prefetching the instruction. According to the method, the instructions are analyzed and classified, the instructions are cached to the corresponding cache regions according to the types of the instructions, and the instruction fetching address of the next instruction is calculated, so that the instruction processing efficiency is effectively improved, the system performance is further improved, and the influence on the system performance due to the increase of read delay is reduced.

Description

technical field [0001] The present application relates to the technical field of data processing, and in particular, to an instruction processing method, device, microcontroller and readable storage medium. Background technique [0002] With the increasing demand for MCUs in the Internet of Things, industrial control, and automotive electronics, MCUs with CORTEX-M series processors as the core have begun to be widely used in the above-mentioned fields. As a microcontroller, MCU pursues more low cost and low power consumption, so the read and write speed of the embedded FLASH or other non-volatile memory used is not high, and it is lower than the access speed of the core. When the core needs to run at a higher clock frequency, it has to increase the read delay for the access to achieve the purpose of correctly accessing the memory. Although increasing the read delay can ensure correct access to the memory, it reduces the maximum performance of the processor. Therefore, modul...

Claims

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Application Information

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IPC IPC(8): G06F9/38G06F12/0862G06F12/0888G06F3/06
CPCG06F9/3806G06F9/3804G06F12/0862G06F12/0888G06F3/061G06F3/0656G06F3/0679Y02D10/00
Inventor 刘吉平陈志豪蒲智星王翔
Owner 深圳市航顺芯片技术研发有限公司
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