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Memory verification unit, method and chip

A memory and sub-unit technology, applied in the computer field, can solve problems such as complex design and limited memory architecture, and achieve the effects of simple implementation, low implementation cost, and high data security level

Pending Publication Date: 2022-05-27
C SKY MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the inline ECC type, the current implementation requires additional memory master support, and the design is complex, which limits the memory architecture

Method used

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  • Memory verification unit, method and chip
  • Memory verification unit, method and chip
  • Memory verification unit, method and chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0023] Based on the bus system, a memory check unit in the embodiment of the present application is as follows: Figure 2A As shown, it includes: a data conversion subunit 102 and a check processing subunit 104 .

[0024] in:

[0025] The data conversion subunit 102 is configured to receive the first transmission data transmitted from the bus to the memory controller, and convert the first transmission data into parity bit width data, wherein the bit width of the parity bit width data is the bus bit width half of .

[0026] The check processing sub-unit 104 is used for inserting check data with the same number of bits as the number of bytes in each check bit width data in every other byte to form a second check data with the same number of bits as the bus bit width. transfer data; send second transfer data to the memory controller.

[0027] In this embodiment, the bus may be a high-bandwidth bus, such as AHB or ASB or AXI in an AMBA bus. Therefore, the memory verification ...

Embodiment 2

[0041] refer to image 3 , showing a flow chart of steps of a memory verification method according to Embodiment 2 of the present application.

[0042] The memory verification method of this embodiment can be implemented by the aforementioned memory verification unit, and the memory verification method of this embodiment includes the following steps:

[0043] Step S202: Receive the first transmission data transmitted to the memory controller from the bus, and convert the first transmission data into parity bit width data.

[0044] The solution of this embodiment can be applied to the system-on-chip of the AMBA bus protocol, especially the high-bandwidth bus, including but not limited to the AXI bus.

[0045] After the memory check unit receives the first transmission data transmitted from the bus, it can convert it into check bit width data, wherein the bit width of the check bit width data is half of the bus bit width. Optionally, the first transmission data may be converte...

Embodiment 3

[0064] refer to Figure 4 , showing a schematic structural diagram of a chip according to Embodiment 3 of the present application.

[0065] The chip in this embodiment at least includes: a processor, a bus, a memory, a memory controller, and the memory check unit described in the first embodiment; wherein: the memory controller is connected between the processor and the memory through a bus; The memory check unit is arranged at the interface of the memory controller.

[0066] In a specific example, as Figure 4 shown, the chip is based on the AMAB bus structure, which in addition to including figure 1 In addition to the high-performance central bus, processor, on-chip memory interface (high-bandwidth external memory interface, used to access on-chip memory), high-performance AI accelerator, DMA, bridge and APB shown in The described kernel check unit and kernel controller.

[0067] It can be seen from the figure that the kernel controller is connected between the on-chip m...

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Abstract

The embodiment of the invention provides a memory verification unit and method and a computer storage medium, and the memory verification unit comprises a data conversion subunit which is used for receiving first transmission data transmitted to a memory controller from a bus, and converting the first transmission data into verification bit width data, the bit width of the check bit width data is half of the bit width of the bus; the check processing subunit is used for inserting check data of which the digit is the same as the byte digit every byte in each check bit width data to form second transmission data of which the digit is the same as the digit of the bus bit width; and sending the second transmission data to the memory controller. Through the embodiment of the invention, additional memory particles do not need to be added, a memory architecture is not influenced, and a high data security level of SEC / DED can be realized every 8 bits. Moreover, the implementation is simple, and the implementation cost is low.

Description

technical field [0001] The embodiments of the present application relate to the field of computer technologies, and in particular, to a memory verification unit, a method, and a computer storage medium. Background technique [0002] Memory verification is a technology for verifying the data read and written to the memory in order to avoid physical attacks on the memory transmission link from the outside world. A commonly used scheme for memory verification is ECC (Error-Correcting Code, error correction code). The ECC scheme operates on 256-byte data each time, including column verification and row verification. XOR each bit to be checked, if the result is 0, it means that it contains an even number of 1s; if the result is 1, it means that it contains an odd number of 1s. If the parity bit is different when data is stored and read and written, it indicates that an error or other abnormality has occurred. [0003] In practical applications, based on the actual storage form ...

Claims

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Application Information

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IPC IPC(8): G06F11/10
CPCG06F11/1004
Inventor 华庆明凌纾
Owner C SKY MICROSYST CO LTD
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