Integrated circuit concurrent test device and method

Abstract

The invention discloses an integrated circuit concurrent test device and method, and the device comprises a test processor TP, a Parameter Pattern compiler PPC, a channel parameter test controller PTC, and an instrument control bus ICB, a new control bus is established between the test processor and a simulation test channel, and the compiling and interpretive execution of the simulation test channel between the test processor and the simulation test channel is realized. Therefore, analog signal testing and digital signal testing are unified into the testing processor, the testing efficiency can be improved, and the testing coverage rate is increased.

Description

technical field [0001] The invention relates to a device and method for concurrent testing of integrated circuits and the field of automatic testing of integrated circuits. Background technique [0002] With the maturity of integrated circuit multi-chip packaging technology and the integration of more digital and analog mixed signals in a single chip, in the integrated circuit automatic test equipment (Auto Test Equipment, referred to as ATE), how to more efficiently test in multiple test stations In the synchronous parallel or asynchronous concurrent test between (Site), complete the mixed test of digital and analog signals, etc., it poses more challenges. For example: in the test of a SOC chip, it is necessary to continuously send trimming data to the chip through the digital channel to the SPI interface, and then test the Ref voltage output through the analog source to find the best trimming value. Because the scale of SOC chips is getting bigger and bigger, and there ar...

AI Technical Summary

Problems solved by technology

1. The test is switched between two processors, resulting in more time spent in the process of switching, and the test efficiency is low

[0004]2. For the test of multiple test stations, since the PC can only serially read the test data through the PCIE bus, it can only simulate each test station serially The signal completes the test, resulting in less efficient testing

However, the timing of the rising edge of the analog pulse signal of each test station is inconsistent, so each test station needs to be able to complete the matching test of the analog signal concurrently and independently, and at the same time, the test of the analog signal needs to be accurately synchronized with the test of the digital signal

In this case, for the traditional test method, because the test of the analog signal needs to be switched to the PC to complete, and the PC can only test serially, and at the same time, it cannot be accurately synchronized with the signal under test, resulting in the inability of each test station to complete the test concurrently

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