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Manufacturing method of multi-die semiconductor device and corresponding multi-die semiconductor device

A semiconductor and bare chip technology, used in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve problems such as low reliability and high manufacturing costs

Pending Publication Date: 2022-06-21
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] It should be noted that implementing die-to-die interconnects by wire bonding, electroless plating, or dispensing of conductive paste can lead to high manufacturing costs and / or low reliability of die-to-die interconnects

Method used

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  • Manufacturing method of multi-die semiconductor device and corresponding multi-die semiconductor device
  • Manufacturing method of multi-die semiconductor device and corresponding multi-die semiconductor device
  • Manufacturing method of multi-die semiconductor device and corresponding multi-die semiconductor device

Examples

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Embodiment Construction

[0020] In the ensuing description, one or more specific details are set forth for the purpose of providing a thorough understanding of the examples of the described embodiments. These embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations have not been illustrated or described in detail so that some aspects of the embodiments will not be hidden.

[0021] References to "an embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in relation to the embodiment is included in at least one embodiment. Thus, the appearance of a phrase such as "in an embodiment" or "in an embodiment" in one or more points of this specification is not necessarily referring to the same embodiment. Furthermore, in one or more embodiments, particular con...

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Abstract

In a method of manufacturing a multi-die semiconductor device, a metal lead frame includes a die pad and a conductive lead disposed around the die pad. The first and second semiconductor dies are disposed on the die pad. A laser activatable material is placed on the die and the leads, and sets of laser activated lines are patterned including a first subset coupling selected bond pads of the die to selected leads, a second subset coupling the selected bond pads to one another, and a third subset coupling lines in the second subset to at least one line in the first subset. A first metal layer is deposited onto the laser activated line to provide a first subset of conductive lines, a second subset of conductive lines, and a third subset of conductive lines. A second metal layer is selectively deposited by electroplating onto the first subset and the second subset to provide a first subset of conductive tracks and a second subset of conductive tracks. The conductive lines in the third subset are selectively removed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority from Italian Patent Application No. 102020000031226 filed on December 17, 2020, the contents of which are hereby incorporated by reference to the fullest extent permitted by law. technical field [0003] This specification relates to multi-die or multi-chip semiconductor devices, which are applicable in various fields such as automotive, industrial, and consumer electronics. Background technique [0004] A conventionally packaged multi-die semiconductor device may include a metal leadframe having a die pad and a set of conductive leads arranged around the die pad (eg, extending radially around the die pad), arranged on the die. A plurality of semiconductor dies on a pad (eg, attached to the die pad) and a plastic package that will be disposed on the die pad and at least a portion of the semiconductor die facing the die pad Conductive lead package. [0005] In such a multi-die semicond...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L21/56H01L23/495H01L23/31H01L25/18H01L25/065
CPCH01L21/50H01L24/82H01L21/56H01L23/49517H01L23/49575H01L23/49541H01L23/3107H01L25/18H01L25/0655H01L2224/82
Inventor P·克雷马
Owner STMICROELECTRONICS SRL
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