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Winding method based on resistance sensitivity

A wire-winding method and wire-winding technology, which are applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve the problems that the network affects the network, unfavorable development of integrated circuit design, failure to consider resistance sensitivity, etc., and achieve the effect of optimal design

Pending Publication Date: 2022-07-01
SEMITRONIX
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The winding algorithm is extremely sensitive to the order of winding, which usually causes the network that is wound first to affect the network that is wound later
[0005] It can be seen from the above that there is currently no winding method that considers resistance sensitivity to meet the needs of different application scenarios, which is also very unfavorable for the further development of integrated circuit design

Method used

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  • Winding method based on resistance sensitivity
  • Winding method based on resistance sensitivity
  • Winding method based on resistance sensitivity

Examples

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Embodiment 1

[0032] like figure 1 As shown, the first embodiment of the present invention discloses a method for winding based on resistance sensitivity, which includes: step S1. Obtaining winding information, including device area, pad area, devices to be wound, and all networks to be wound; such as figure 2 shown, wherein the device to be wound is in the device area; there are several pads in the pad area, and one side of the pad area and one side of the device area share the same edge; the The to-be-wound network includes pads and pins to be connected by the wire, and the pins are on the to-be-wound device; preset wire width and wire interval; step S2. Divide the device area into device grids and an area grid, the area grid includes a first grid and a second grid; such as Figure 3-5 As shown, the device grid is a grid generated by expanding the location area of ​​the device to be wound; the first grid is a grid created in the device area between the device grid and the pad area Grid...

Embodiment 2

[0038] In this embodiment, the device area between two adjacent first grids is created as a second grid; let the two adjacent first grids be zone1 and zone2 respectively from bottom to top, and the position information of zone1 is (zone1_x1, zone1_y1, zone1_x2, zone1_y2), the location information of zone2 is (zone2_x1, zone2_y1, zone2_x2, zone2_y2), then the location information of the second grid: free_zone_x1=da_x1; free_zone_x2=da_x2-space; free_zone_y1=zone1_y2; free_zone_y2=zone2_y1.

Embodiment 3

[0040] In this embodiment, the device region between the lower edge of the device region and the bottommost first grid is created as a second grid; the bottommost first grid is set as zone0, and the position information of zone0 is (zone0_x1, zone0_y1 , zone0_x2, zone0_y2), then in the position information of the second grid: free_zone_x1=da_x1; free_zone_x2=da_x2-space; free_zone_y1=da_y1; free_zone_y2=zone0_y1.

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Abstract

The invention provides a winding method based on resistance sensitivity. The winding method comprises the steps that winding information is acquired; dividing the device area into a device grid and an area grid; acquiring information of the regional grids; and creating a winding path of the to-be-wound network according to the regional grids. And resistance sensitivity is considered during winding, so that the winding requirement in a required scene can be met, the winding success rate can be improved, and the design can be optimized.

Description

technical field [0001] The invention belongs to the field of semiconductor design and production, and in particular relates to a resistance-sensitive-based wire winding method. Background technique [0002] With the rapid development of integrated circuit technology, integrated circuits have entered the ultra-deep sub-micron era, which makes the feature size of electronic devices smaller and smaller, the scale of chips larger and larger, and more and more components can be integrated in a single On the chip, the complexity has risen sharply, and for the wiring method in the layout, the manual design wiring method has long been unable to meet the needs of integrated circuit design. The quality directly affects the realization of the function and the quality of the electrical performance. The routing algorithm has an extremely important influence on the speed and efficiency of the routing. How to design an algorithm with less time and space, lower complexity and higher effici...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/394G06F30/398
CPCG06F30/394G06F30/398
Inventor 邵康鹏彭焱
Owner SEMITRONIX
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