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Preparation method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device preparation, can solve the problems of different high temperature resistance requirements, inability to adapt to wafers, etc.

Pending Publication Date: 2022-07-15
浙江同芯祺科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Most of the existing wafer preparation lines are wafer preparation lines of a single size (such as 8 inches), which cannot adapt to wafers of other sizes (such as 6 inches)
Moreover, during the wafer preparation process, high-temperature steps such as high-temperature ion activation and trench oxidation are involved, which have different high-temperature resistance requirements for the carrier plate, the carrier plate, and the sealing material. The existing technology cannot effectively solve the above problems

Method used

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  • Preparation method of semiconductor device
  • Preparation method of semiconductor device
  • Preparation method of semiconductor device

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preparation example Construction

[0034] like figure 1 As shown, a method for fabricating a semiconductor device according to an embodiment of the present invention includes:

[0035] A100, such as figure 2 and image 3 As shown, the epitaxial layer 20 is prepared on the surface of the SiC substrate 10 and then placed on a Si-based carrier 30 with a preset size;

[0036] It should be noted that when the SiC substrate 10 is placed on the Si-based carrier 30 , the subsequent preparation process can be performed under the support of the Si-based carrier 30 , and the size of the SiC substrate 10 can be the same as that of the Si-based carrier 30 . Differently, by selecting Si-based carrier discs 30 of different sizes, it is possible to adapt to the equipment on the assembly line of different sizes, and make full use of the existing assembly line processing equipment to process semiconductor devices.

[0037] A200, performing ion implantation in the epitaxial layer 20;

[0038] like Figure 4 and Figure 5 A...

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Abstract

The invention provides a preparation method of a semiconductor device. The preparation method comprises the following steps: A100, preparing an epitaxial layer on the surface of a SiC substrate and then placing the SiC substrate on a Si-based carrier plate with a preset size; a200, carrying out ion implantation on the epitaxial layer; a300, preparing a coating layer on the surface of the epitaxial layer after ion implantation; a400, after the SiC substrate is separated from the Si-based carrier plate, a high-temperature ion activation process is carried out; and A500, removing the coating layer, depositing and preparing a grid electrode and a dielectric layer on the surface of the epitaxial layer, opening the contact hole and placing the SiC substrate back to the Si carrier after groove oxidation is completed. According to the invention, the SiC substrate is arranged on the Si-based carrier plate with the preset size, so that the processing equipment of the existing semiconductor device size can be fully utilized, and the equipment replacement cost is reduced. Moreover, in the preparation process of the semiconductor device, when a high-temperature operation step is involved, the SiC substrate is separated from the Si-based carrier plate, so that the Si-based carrier plate and the sealing layer are prevented from being damaged by high temperature. The preparation method is convenient to operate and reasonable in process.

Description

technical field [0001] The invention relates to the technical field of wafer processing and preparation, in particular to a preparation method of a semiconductor device. Background technique [0002] For semiconductor devices, for example, in the process of wafer processing and preparation, the thinness of the wafer is small, and the processing process usually needs to be carried out under the support of a carrier plate or a carrier plate. Most of the existing wafer preparation lines are wafer preparation lines of a single size (eg, 8 inches), which cannot be adapted to wafers of other sizes (eg, 6 inches). Moreover, in the wafer preparation process, high temperature steps such as high temperature ion activation and trench oxidation are involved, which have different high temperature resistance requirements for the carrier plate, the carrier plate and the sealing material, and the above problems cannot be effectively solved by the prior art. SUMMARY OF THE INVENTION [00...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/683H01L21/04H01L21/265H01L21/324
CPCH01L21/6835H01L21/0445H01L21/26506H01L21/324H01L2221/68313
Inventor 严立巍文锺符德荣
Owner 浙江同芯祺科技有限公司