Method and device for automatically adaptively extracting chip ECID

A chip and adaptation technology, applied in natural language data processing, instruments, data processing applications, etc., can solve the problems of large test volume, difficult data location, huge STDF file, etc., to improve the yield rate. Effect
CN114780802AActive Publication Date: 2022-07-22江苏泰治科技股份有限公司
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
江苏泰治科技股份有限公司
Publication Date
2022-07-22

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Abstract

The invention discloses a method and device for automatically extracting chip ECID in an adaptive mode, and belongs to the field of semiconductor testing. The method comprises the following steps: acquiring information associated with an ECID from a test program and a test data file, and constructing a method configuration table and an access configuration table; importing batch data to be analyzed, obtaining a first information set, and obtaining matched access method indication and decoding method indication from the method configuration table according to the first information set; acquiring multiple groups of access logics from the access configuration table according to the access method indication, and acquiring matched ECID related original data from the to-be-analyzed data according to the access logics; the method comprises the following steps: processing ECID related original data by using a decoding method to obtain FABLOT information, WAFERNUM information and DIEX / DIEY information corresponding to each chip; and splicing according to a rule to obtain the ECID. According to the invention, the ECID of the chip can be quickly obtained, and the test efficiency can be improved.
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Description

technical field

[0001] The invention belongs to the technical field of semiconductor testing, and in particular relates to a method and a device for automatically adapting and extracting the ECID of a chip. Background technique

[0002] After a wafer is fabricated, thousands of bare DIEs (unpackaged chips) are regularly distributed on the wafer. These chips in the industry have their own unique numbers, namely ECID (Exclusive Chip ID). The ECID of a chip consists of three parts: FABLOT: fab lot number, WAFERNUM: wafer number, DIEX / DIEY: the horizontal and vertical coordinates of the chip on the wafer. Based on this information, the specific testing situation of each chip at different test sites (including CP (ChipProbe), FT (Final Test)) and different test stages (initial test, retest) can be tracked. Therefore, in the semiconductor industry, when chip testing companies and chip design companies check defective chips, they can quickly locate the testing process of defective...

Claims

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