Device for improving gate driving capability and manufacturing method thereof

Abstract

The invention discloses a device for improving gate driving capability and a manufacturing method thereof. The method comprises the steps of manufacturing an epitaxial layer on the upper side of a substrate; forming a plurality of P-type Ring regions in the epitaxial layer; growing a field oxide layer on the upper side of the epitaxial layer and etching; growing a gate oxide layer on the upper side of the epitaxial layer which is not covered by the field oxide layer, depositing P-type element doped polycrystalline silicon on the upper side of the gate oxide layer, and then etching to form a polycrystalline silicon resistor, a polycrystalline silicon gate of a PMOS (P-channel Metal Oxide Semiconductor), a polycrystalline silicon gate of an NMOS (N-channel Metal Oxide Semiconductor) and a polycrystalline silicon gate of a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor); a VDMOS cut-off ring region is formed at the outer end of the epitaxial layer, meanwhile, an NMOS cut-off ring region, an NMOS source region and a VDMOS source region are formed in the Ring region, and injection doping is carried out on a polysilicon gate of the NMOS and a polysilicon gate of the VDMOS. The device can be quickly started and turned off in a delayed manner, high-frequency oscillation is eliminated, the stability of the device is improved, the power loss is reduced, and the packaging cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a device with improved gate drive capability and a manufacturing method thereof. Background technique [0002] The existing MOS is usually directly connected to the IC circuit as a driver after the gate is connected in series with a resistor Rg. Rg is strongly related to the on-off speed of the switching device: small resistance, fast on-off speed, and low loss. This method has the following disadvantages: 1) Too fast driving speed will greatly increase the voltage and current rate of change of the MOS, resulting in greater interference, which may seriously cause the entire device to fail to work; 2) If the parasitic capacitance of the MOS itself is large , the energy required to turn on the MOS will also increase accordingly. If the IC driving ability is insufficient, high-frequency oscillation may occur on the rising edge, and it is difficult to eliminate Rg; Swi...

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Problems solved by technology

This method has the following disadvantages: 1) If the driving speed is too fast, the voltage and current change rate of the MOS will be greatly increased, resulting in greater interference, which may seriously cause the entire device to fail to work; 2) If the parasitic capacitance of the MOS itself is large , the energy required to turn on the MOS will also increase accordingly. If the IC driving ability is insufficient, high-frequency oscillations may occur on the rising edge, and it is difficult to eliminate it even if the Rg is reduced; and the IC driving ability is insufficient, the turn-on speed of the MOS will also slow down, increasing Switching loss; 3) Combined with factors such as IC drive capability, MOS parasitic capacitance, switching speed, etc., Rg cannot be infinitely reduced

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