Clock synchronization method, device, system and equipment for chip testing

Abstract

The invention relates to a clock synchronization method, device, system and equipment for chip testing. The method comprises the following steps: generating a synchronous clock signal of a target frequency by responding to an instruction for carrying out clock synchronization among a plurality of target measurement board cards and configuring a dynamic reconfiguration register in a phase-locked loop in a field programmable logic gate array on a backboard through a bus protocol; and outputting the synchronous clock signal to a clock input pin of a field programmable logic gate array on the target measurement board card. According to the embodiment of the invention, the dynamic reconfiguration register in the existing phase-locked loop on the backboard is utilized to output the synchronous clock signals to a plurality of target measurement board cards at the same time, and a special clock chip is not needed; and the dynamic reconfiguration register in the phase-locked loop is configured through the bus protocol, so that the configuration speed is high, the cost is low, input/output pins in the field programmable logic gate array are not occupied, and the area of a printed circuit board is reduced.

Description

technical field [0001] The present disclosure relates to the technical field of chip testing, and in particular, to a clock synchronization method, apparatus, system and device for chip testing. Background technique [0002] The digital chip tester usually uses the pattern (sequence characteristic) test to judge whether the chip function is normal, so as to realize the rapid test when the digital chip is mass-produced. The digital chip tester generally supports hundreds of pattern test channels, such as 512, 768, 1024 channels, etc. The pattern digital waveform output by each channel needs to be output to the pins of the digital chip to be tested at the same time, that is, the pattern digital waveform needs an edge Alignment to ensure that the timing between the signals output to the pins of the digital chip under test is correct. To ensure that the digital waveforms output by all pattern channels of all digital chip testers are edge-aligned, the clocks of each digital meas...

AI Technical Summary

Problems solved by technology

The slow speed of SPI interface configuration results in longer test time; the dedicated clock chip occupies the I/O (Input/Output, input/output) pin resources of the FP

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