Exposure mask and its mfg. method
A manufacturing method and mask technology, applied in semiconductor/solid-state device manufacturing, optics, optomechanical equipment, etc., can solve problems such as difficult to eliminate aspect ratio problems and connection problems between graphics, and achieve the elimination of connection problems between graphics, eliminate Aspect Ratio Issues, Effects of Elimination of Ring Issues and Vane Issues
Inactive Publication Date: 2004-11-24
NEC ELECTRONICS CORP
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Problems solved by technology
As in the technology described in the above publication, it is difficult to solve these aspect ratio problems and connection problems between patterns by simply dividing the mask pattern into X-direction components and Y-direction components.
Method used
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[0030] Hereinafter, embodiments of the present invention will be described with reference to the drawings. figure 2 It is a detailed flowchart showing the manufacturing method of the exposure mask of this invention in order of process. refer to image 3 The flow chart will be described with an example of a mask pattern of the pattern shape shown. First, in the source / drain region 102 formed on the semiconductor wafer 101, in the state where the gate pattern for forming the MOS transistor TR is extended in the Y direction, the image 3 The mask patterns P00 are arranged in parallel in the X direction. One end of each gate pattern 103 is extended to an impurity region 104 forming a PN junction of the diode D formed on the semiconductor wafer 101 . In addition, the Y-direction connection wiring 105 is arranged in parallel with the above-mentioned gate pattern 103 . Moreover, each of the gate patterns 103 described above is connected to each other through one end portion and ...
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PROBLEM TO BE SOLVED: To solve doughnut problem, leaf problem, aspect ratio problem, and inter-pattern connection problem which occur in a stencil mask. SOLUTION: It is judged whether a doughnut problem, a leaf problem, or an aspect ratio problem occurs in a mask pattern, the mask pattern is divided into two patterns, when it is found that a problem occurs, and the two patterns are allotted to two masks. When one of the problems occurs, the pattern of one of the masks is partially allotted to the other mask. When no doughnut problem and no leaf problem occur, it is determined for each mask as to whether an aspect ratio problem occurs, when it is found that an aspect ratio problem has occurred, the pattern of one of the masks is partially allotted to the other mask. When it is found that no aspect ratio problem occurs, it is determined whether a connection failure occurs to a pattern connection, and when it is found that a connection failure has occurred, an auxiliary pattern is provided to a pattern connection.
Description
technical field [0001] The present invention relates to an exposure mask for pattern exposure using charged particle beams such as electron beams and ion beams, and a method for manufacturing the same. Background technique [0002] In recent years, with the high integration of semiconductor devices, the patterns exposed on semiconductor wafers have also been miniaturized. For the exposure of such fine patterns, exposure methods using charged particle beams such as electron beams and ion beams are used. In addition, in order to increase the throughput of pattern exposure, the technology of controlling the charged particle beam within the required beam area and exposing patterns by batches or as a whole is also being developed. For example, in batch exposure, the beam area on the wafer is set to about 5 μm2, while in bulk exposure, the beam area on the wafer is set to about 250 μm2, and the mask is irradiated with the beam in such an area unit to perform exposure. . In expos...
Claims
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Login to View More IPC IPC(8): G03F1/20G03F7/00H01L21/027
Inventor 小日向秀夫
Owner NEC ELECTRONICS CORP