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Method for locally forming silicide metal layer

A technology for silicided metal layers and metal layers, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., and can solve problems affecting memory efficiency and leakage current, etc.

Inactive Publication Date: 2005-02-16
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This will cause leakage current, which will affect the efficiency of the memory

Method used

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  • Method for locally forming silicide metal layer
  • Method for locally forming silicide metal layer
  • Method for locally forming silicide metal layer

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Embodiment Construction

[0012] Preferred embodiments of the present invention will be discussed in detail as follows. These embodiments are used to describe a specific example of using the present invention, but not to limit the scope of the present invention.

[0013] The present invention provides a method to form a metal silicide in a local area on an integrated circuit, which includes the following steps: first, as Figure 3A As shown, a substrate 100 is provided, and there are two regions on it, one is the array region 101 and the other is the peripheral region 102 . A first dielectric layer-second dielectric layer-first dielectric layer (ONO) layer 105 is deposited on the array area 101, and a memory array is placed on the ONO layer 105, and the memory gate 110 is the same There is a first spacer region 306 between two adjacent memory gates on the word line. The peripheral region 102 includes at least transistor gates 120 , and a second spacer region 307 is located between two adjacent transi...

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Abstract

The invention discloses the method for forming the siliconized metal layer locally on the integrated circuit, but prevents the formation of the siliconized metal layer between the memories in the same word line so as to cause the phenomena of the electric leakage. The proper interval between the components is designed to reach the said requirement. The dielectric layer in the interval area between the adjacent two memories is formed as the mask layer in advance. In the sequential selective etching steps, the silicon substrate in the said interval area is protected so as to prevent the area to be exposed. Thus, the siliconized metal will not be formed at the said interval so as to realize the purpose.

Description

Field of invention: [0001] The present invention relates to a method for partially forming a metal silicide layer, in particular to a method for locally forming a metal silicide layer for avoiding leakage current between memories. Background of the invention: [0002] In order to reduce the resistance value and improve the efficiency of the integrated circuit, a metal silicide layer, such as silicon titanium oxide, is often deposited on the surface of the circuit and the device. It is necessary to avoid the formation of metal silicide on the surface of the area that is not suitable for lowering the resistance value, such as the spacer area between the memories on the same word line. Traditional formation methods such as figure 1 As shown: First, there is a silicon substrate 100 , and on the substrate 100 , there are at least two regions: one is an array region 101 , and the other is a peripheral region 102 . In the array area 101, there is a dielectric layer 105, such as a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3205H01L21/4763H01L21/784
Inventor 陈盈佐赖二琨陈昕辉黄守伟黄宇萍
Owner MACRONIX INT CO LTD
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