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Method for realizing 16b/20b encoder logic based on double 8b/10b encoder

A kind of encoder and encoding technology, applied in the direction of digital transmission system, electrical components, transmission system, etc., can solve problems such as mitigation

Inactive Publication Date: 2007-02-14
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

However, the problem with this scheme is that the wires that implement run-length inheritance actually cross the two-phase clock domains, thus becoming critical paths for timing
Moreover, this timing requirement must be met, and it cannot be alleviated by adding latches.

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  • Method for realizing 16b/20b encoder logic based on double 8b/10b encoder
  • Method for realizing 16b/20b encoder logic based on double 8b/10b encoder
  • Method for realizing 16b/20b encoder logic based on double 8b/10b encoder

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[0013] Specific implementation methods: such as figure 1 As shown, Z0 and Z1 are 9 bits of data to be encoded respectively, each of which includes a command control signal key. Y is an output of 20 bits of encoded data, which meets the limit of the maximum run length offset. Encoder-0 (encoder: encoder) and Encoder-1 are two 8b / 10b encoders (2, 3) with exactly the same logic structure, both of which have forced run offset enable terminal (force_disp) and run offset input end (disp_in), and the forced run length offset enable end is always set to the active state ('1'). General programmable logic device suppliers will provide mature 8b / 10b IP-Core to users. in addition, figure 1 There is a word order selection signal input Endian (endian, that is, the order of high-order or low-order first of multi-bit data), which is '1' to indicate that the output of the Encoder-1 encoder is in front, and '0' to indicate that the Encoder -0 The output of the encoder comes first. Fore-Code...

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Abstract

The invention relates to a method for realizing 16b / 20b encoder logic based on double 8b / 10b encoders, wherein a 16b / 20b encoder is constructed on the basis of two 8b / 10b encoders, which solves the problem of time sequence stress of 16b / 20b encoder constructed from two 8b / 10b encoders when being used for DDR data source.

Description

technical field [0001] The present invention relates to the technical field of digital communication, especially a kind of 16b / 20b encoder logic realization method based on double 8b / 10b encoder, especially use two 8b / 10b encoder modules to add a small amount of logic to form a kind of suitable for DDR ( Double Data Rate, double-edge data rate) data transmission and a 16b / 20b encoder implementation method that meets the requirements of the run-length balance specification. Background technique [0002] The 8b / 10b coding scheme and its implementation method are the technical results of the 1980s. Because it conveniently controls the DC component on the serial transmission line, it is widely used in the field of communication technology, such as optical fiber communication devices, serial-to-parallel conversion place. Under the 8b / 10b encoding specification, when the output 10-bit data is serialized and transmitted, there will be no 6 consecutive '0' or 6 consecutive '1' on t...

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Application Information

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IPC IPC(8): H04L5/00H04L7/00
Inventor 高文学安学军杨晓君苗彦超吴冬冬张佩珩
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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