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SRAM unit with multi-grid transistor and mfg method thereof

A technology for static random access and memory cells, which is applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., and can solve problems such as increasing the complexity of circuit design

Inactive Publication Date: 2007-02-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this will increase the complexity of the circuit design

Method used

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  • SRAM unit with multi-grid transistor and mfg method thereof
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  • SRAM unit with multi-grid transistor and mfg method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0103] Structure of SRAM memory cell

[0104] Figure 6C It is a layout diagram of a SRAM memory cell according to a first embodiment of the present invention, which includes the relative configuration relationship of island-shaped semiconductor active regions, source electrodes, drain electrodes, contact window plugs and gate electrodes.

[0105] A 6T-SRAM memory cell basically includes a pair of pull-up transistors PU1 and PU2, a pair of pull-down transistors PD1 and PD2, and a pair of access transistors PG1 and PG2. The pull-up transistors PU1 and PU2 are usually p-channel field effect transistors (PFETs) arranged in the n-type well region NW, and the pull-down transistors PD1 and PD2 and the access transistors PG1 and PG2 are usually n-channel field effect transistors (PFETs) arranged in the p-type well region PW. Channel Field Effect Transistor (NFET).

[0106] The above six transistors are multiple-gate transistors disposed in the island-shaped semiconductor active are...

no. 2 example

[0159] Structure of SRAM memory cell

[0160] Figure 13B It is a layout diagram of an SRAM storage unit according to a second embodiment of the present invention.

[0161] The six transistors in the 6T-SRAM are multi-gate transistors disposed in the island-shaped semiconductor layer 64, such as double-gate transistors (see Figure 7A and Figure 7B ), triple gate transistors (see Figure 8A and Figure 8B ), or Ω-shaped multiple-gate transistors (see Figure 9A and Figure 9B ). Figure 14 It is a perspective view showing the relative arrangement relationship between the island-shaped semiconductor active region and the gate electrode of the access transistor PG1 and the pull-down transistor PD1 composed of double-gate transistors. Figure 15 It is a perspective view showing the relative arrangement relationship between the island-shaped semiconductor active region and the gate electrode of the access transistor PG1 and the pull-down transistor PD1 composed of triple g...

no. 3 example

[0174] Structure of SRAM memory cell

[0175] Figure 16 It is a layout diagram of an SRAM storage unit according to a third embodiment of the present invention. Different from the second embodiment, the island-shaped semiconductor active regions AA of each transistor are separated from each other, and then electrically connected by contact plugs. The numbers in the figure are used Figure 13B The label of , will not be explained here.

[0176] Impedance ratio of pull-down transistor and access transistor (β)

[0177] In the above example, the case where each strip structure in the island-shaped semiconductor active region AA is equal in width and height is taken as an example. Of course, its width and height can be changed depending on the actual layout considerations. But usually the height will be equal due to the convenience of the manufacturing process. In addition, generally, the bottom contribution width of the island-shaped semiconductor layer 64 is also equal in...

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Abstract

This invention discloses a SRAM unit with multiple grids transistors which changes the channel width of a transistor and increases beta ratio value of pulling and access transistors by using a multigrid transistor, eg. a double-grid transistor, three-grid transistor and a omega shape multiple transistor. This invention also discloses a manufacturing method for a SRAM unit with a multigrid transistor.

Description

technical field [0001] The present invention relates to a static random access memory (static random access memory; SRAM), and in particular to a multi-gate field-effect transistor (multiple-gate field-effect transistor; MGFET) with better stability static random access memory unit (SRAM cell). Background technique [0002] SRAM is a common memory, and it is a volatile memory, that is, when the power supplied to the SRAM disappears, the stored data will be erased at the same time. The way SRAM stores data is achieved by using the conductive state of the transistor in the memory cell. The design of SRAM is based on mutual coupling transistors, there is no problem of capacitor discharge, and it does not need to be continuously charged to keep data from being lost, that is, There is no need to update the memory, which is different from the dynamic random access memory (DRAM), which is also a volatile memory, by using the charged state of the capacitor to store data. The acces...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11H01L21/8244H01L21/336H01L21/8239H01L21/8242H01L27/10H01L27/12H01L29/423H01L29/786
CPCH01L29/785H01L27/1104H01L29/66795H01L27/11H01L27/1211H01L29/42384H10B10/00H10B10/12
Inventor 杨育佳胡正明杨富量
Owner TAIWAN SEMICON MFG CO LTD
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