64 results about "Triple gate" patented technology

A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

The invention provides a display drive chip, a display drive chip assembly and a display device, belongs to the field of the display technology, and can solve the problem, caused by unmatched impedances, of poor displaying of the conventional display device. The display drive chip provided by the invention comprises a plurality of output ports and a drive circuit, wherein the output port are used for outputting drive signals; the drive circuit is used for generating drive signals and connected with the output ports; a chip impedance matching unit with a certain impedance is arranged between at least one output port and the drive circuit. The invention can be used in a display device adopting an active drive array such as an LCD device and an organic LED display device, is particularly applicable to display devices adopting technologies of narrow frame, dual gate, triple gate and high frequency drive.

A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

The invention provides a semiconductor device and fabrication methods thereof. The semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

A microwave radio frequency (RF) front end module (FEM) having a low noise amplifier (LNA) with a bypass mode uses a single-pole-triple-throw RF switch that reduces insertion loss to about 1 dB and thereby improves RF receiver sensitivity over existing technology two series connected single-pole-double throw RF switches. The single-pole-triple-throw RF switch may be three metal oxide semiconductor field effect transistor (MOSFET) RF switches that may be arranged with a common source input and isolated independent drain outputs. The RF switches may be single, double or triple gate MOSFET RF switches. The MOSFET RF switches may also be configured as complementary metal oxide semiconductor (CMOS) field effect transistor (FET) RF switches.

A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.

Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region, a second region and a third region, forming a first oxide film and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, forming a third oxide film on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film and forming a fourth oxide film on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure is formed in the first region, a gate oxide having a double structure is formed in the second region and a gate oxide having a double structure is formed in the third region.

The invention relates to the technical field of communication of RS485 buses, in particular to an RS485 bus interface circuit. The technical scheme is that: a differential signal transmission circuit section of an RS485 interface consists of a triode inverter, two sets of push-pull type inverting amplifiers and four triple gates, wherein the output end of the triode inverter is connected to the two push-pull signal input ends of a first set of push-pull type inverting amplifier through a first triple gate and a second triple gate respectively; the output end of the first set of push-pull typeinverting amplifier is connected with a first differential signal wire RS485A; and a direct signal of a second set of push-pull type inverting amplifier is communicated with the input end of the triode inverter and a second differential signal wire RS485B. Through the two sets of push-pull type inverting amplifiers, an RS485 differential signal can be output, and the power of an output signal is effectively improved, so that the communication distance in the scheme can reach 2,000 m, 64 transceivers can be hung, and the communication rate can reach 9,600 bps.

A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a MOS and a nMOS with a triple gate insualting film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a MOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the PMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.

To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.