Method for forming gate of semiconductor device

Abstract

A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode.

Description

[0001] related application [0002] This application claims priority from Korean Patent Applications 10-2008-0054886, 10-2008-0054892, and 10-2008-0100229 filed on June 11, 2008, June 11, 2008, and October 13, 2008, respectively, They are incorporated herein by reference. technical field [0003] The present invention relates to a semiconductor manufacturing technology; more particularly, to a method of forming a gate of a semiconductor device. Background technique [0004] As the integration density of semiconductor devices increases, the channel length of transistors decreases, and the density of sources and drains gradually increases. Therefore, severe interference between source and drain leads to short-channel effects that reduce threshold voltage and increase leakage current. In order to suppress the short channel effect, extensive research has been conducted on a tri-gate type transistor and a recessed gate type transistor in which the transistor has a polyhedral ch...

AI Technical Summary

Problems solved by technology

[0013] First, plasma damage leads to crystal defects

If crystal defects caused by plasma damage occur in side A serving as a channel, device characteristics deteriorate

In particular, the reliability of the device decreases

[0014] Second, the use of the plasma etching process deteriorates the surface roughness, such as striations that inevitably form in side A during the plasma etching process

Therefore, the failure of the gate oxide layer is caused, or the lifetime of the gate oxide layer is reduced

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