Semiconductor memory device

Abstract

A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

Description

[0001] This application is a divisional application of the invention patent application with the application number 98119535.0 and the invention title "Semiconductor Integrated Circuit Device Including Memory Device". technical field [0002] The present invention relates to a semiconductor memory device, and more particularly, to a technique effectively applicable to a semiconductor integrated circuit device with DRAM (Dynamic RAM). In the following description, an n-channel MOSFET is abbreviated as "nMOS" and a p-channel MOSFET is abbreviated as "pMOS". Background technique [0003] The number of bits of DRAM has been increasing. This is because FRAM has characteristics suitable for increasing integration. For example, in all kinds of semiconductor memories, the cell structure of DRAM is quite simple, the pattern design has been regularized so that it is possible to design DRAM on a large scale, and the cell area can be made small; wait. [0004] As the number of bits of...

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Problems solved by technology

This structure also makes it difficult to obtain a positional margin between the capacitor 56 and the capacitor connection conductor 57 (a portion for obtaining electrical connection with the source or drain of the MOS) adjacent to each other.

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