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Digital frequency control circuit, phase control circuit, pll circuit

A phase control circuit and circuit technology, applied in the direction of automatic power control, electrical pulse generator circuit, and logic circuit to generate pulses, etc., can solve the upper limit of sampling frequency, digital calculation and processing range limitation, etc., to achieve improved accuracy Effect

Inactive Publication Date: 2007-04-04
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this real-time processing, the range of numerical calculations and processing that can be performed is limited
In other words, since all processing must be performed within one sampling period, the upper limit of the sampling frequency is limited

Method used

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  • Digital frequency control circuit, phase control circuit, pll circuit
  • Digital frequency control circuit, phase control circuit, pll circuit
  • Digital frequency control circuit, phase control circuit, pll circuit

Examples

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no. 1 example

[0059] Fig. 1(A) shows a digital PLL circuit in a first embodiment according to the present invention.

[0060] This circuit is provided with a digital frequency control circuit 10, a digital phase control circuit 20, and an oscillation circuit 30.

[0061] The first feature of this digital PLL circuit is that it uses an oscillating circuit 30 as shown in Fig. 1(B), which outputs a signal whose period T can be expressed as a linear function of the control input value S . For example the period T is expressed as

[0062] T=k(S-Sc)+Tc, (1)

[0063] Among them, k, Sc and Tc are constants.

[0064] The oscillation frequency fo of the oscillation circuit 30 is expressed as

[0065] fo=1 / T. (2)

[0066] The oscillating circuit can be constructed in such a way that the input of an inverter is connected via a delay circuit to the output of an inverter, so that the time delay of this delay circuit is adjusted corresponding to the value S of the control input. An example of this i...

no. 3 example

[0141] Fig. 13 shows a digital PLL circuit according to the present invention in a third embodiment.

[0142] In the digital frequency control circuit 10B, by loading -Tc / K+Sc to the counter 12 instead of clearing the counter 12, the calculation circuit 13 in FIG. 1(A) is omitted.

[0143] In other respects, the third embodiment is the same as the first embodiment.

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Abstract

An oscillating circuit (30) outputs a signal phio whose pulse cycle T is a linear function T=kS+m of a control input value S. A frequency control circuit (10), every time a counter (11) counts a number Nr of pulses of a reference signal phir, calculates S=No-m / k, where No is a count of phio counted by the counter (12), makes a judgement on convergence of phio based upon the difference between input and output values of a register (14). A digital phase control circuit (20) judges a advance / delay of the phase of phio relative to phir with a phase comparator circuit (21), when the result of the judgement on the advance / delay of the phase is reversed from the previous result of that, changes the count to a value that is half the number of times that the same judgement was made successively before the reversal.

Description

[0001] The present invention is a divisional application of the patent application filed on August 20, 1996 with the application number 96111142.9 and titled "Digital Frequency Control Circuit, Phase Control Circuit and PLL Circuit". technical field [0002] The present invention relates to a digital phase control circuit and a digital phase-locked loop (PLL) circuit having one of these circuits, and to a semiconductor integrated circuit having one of these circuits. Background technique [0003] In an analog PLL circuit, if noise is added to the input of a voltage-controlled oscillator (VCO), the frequency and phase of its output change. Since a low voltage source is used in a PLL circuit operating at a high frequency, the noise margin becomes narrow. These factors make it very difficult to increase the accuracy of an output signal in an analog PLL circuit whose upper limit is about 100 MHz. [0004] On the other hand, in digital PLL circuits, there are digital logic circu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H03L7/085H03L7/113H03K3/03H03L7/06H03L7/087
CPCH03L7/085H03L7/113H03L7/08H03K3/03
Inventor 高石彻
Owner SOCIONEXT INC