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Non-volatile semiconductor memory device, electronic card and electronic device

A non-volatile, storage device technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, information storage, etc., can solve the problems of increasing the size and area of ​​the component isolation insulating film, and achieving the effect of reducing the size

Inactive Publication Date: 2007-04-18
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, since the size of the element isolation insulating film is increased, the area of ​​the region where the transfer transistor is arranged (that is, the area of ​​the row decoder) becomes larger.

Method used

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  • Non-volatile semiconductor memory device, electronic card and electronic device
  • Non-volatile semiconductor memory device, electronic card and electronic device
  • Non-volatile semiconductor memory device, electronic card and electronic device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0053] 1. The structure of NAND cell

[0054] 2. Action of NAND unit

[0055] (1) General operation example of NAND unit

[0056] (2) Comparative example

[0057] (3) Example of operation of the NAND cell according to the first embodiment

[0058] 3. Features of the first embodiment

[0059] (Feature 1)

[0060] (Feature 2)

[0061](Feature 3)

[0062] (Feature 4)

[0063] (Feature 5)

no. 3 Embodiment

[0066] (applicable to electronic cards and electronic devices)

[0067] In addition, in the drawings for explaining the respective embodiments, the same members as those indicated by the symbols in the drawings already described are given the same reference numerals and their descriptions are omitted.

[0068] (first embodiment)

[0069] 1. The structure of NAND cell

[0070] FIG. 1 is a schematic cross-sectional view of a NAND cell included in the NAND-type EEPROM according to the first embodiment. FIG. 2 is a schematic view of the II(a)-II(b) section in FIG. 1 . FIG. 3 is an equivalent circuit diagram of the NAND cell of FIG. 1 .

[0071] As shown in Figures 1 to 3, NAND cell 1 has - A structure of 16 memory cells MC0 to 15 is formed on the type semiconductor substrate 3 . A memory cell is a nonvolatile cell in which data can be electrically rewritten. Each memory cell has the same structure, taking the memory cell MC0 as an example, it includes: n cells formed on the ...

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PUM

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Abstract

Provided is a NAND type EEPROM which can reduce the area of a region in which a transfer transistor is disposed. A nonvolatile semiconductor memory device includes word lines WL0-15 connected to memory cells disposed in a block BK and connected to impurity regions 41 of the transfer transistors Q0-15. Drive lines DL0-15 for supplying a voltage to the word lines WL0-15 are connected to the impurity regions 43 of the Q0-15. In order to write data in the memory cell connected to the word line WL3, 20V is applied to the word line WL3, and 0V is applied to the word lines WL1, 5 of two adjacent word lines. The transfer transistors Q1, 5 of the word lines WL1, 5 are not disposed adjacently and oppositely to the transfer transistor Q3 of the word line WL3. Thus, a potential difference between the adjacent transfer transistors is prevented from becoming large.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data, for example, to a NAND type EEPROM. Background technique [0002] Conventionally, an EEPROM capable of electrically rewriting data is known as one of semiconductor memories. Among them, a NAND-type EEPROM having a plurality of NAND cells configured by serially connecting a plurality of memory cells that store 1 bit has attracted attention as an element that can be highly integrated. The NAND type is used, for example, in memory cards for storing image data of digital still cameras. [0003] The NAND-type EEPROM memory has a FET-MOS structure in which floating gates and word lines are laminated on a semiconductor substrate serving as a channel region through an insulating film. NAND cells are formed by serially connecting a plurality of adjacent memory cells with shared source / drain. The so-called source / drain refers to an impurity regio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/10H01L27/115G11C16/06G11C8/00G11C16/04G11C16/10G11C16/12H01L21/8247H01L29/788H01L29/792
CPCG11C16/0483G11C16/10
Inventor 二山拓也细野浩司
Owner TOSHIBA MEMORY CORP