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Wafer-class packaging technology and its chip structure

A wafer-level packaging and manufacturing process technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problem of different thermal expansion coefficients of wafers and substrates

Inactive Publication Date: 2007-05-09
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The second purpose of the present invention is to provide a wafer-level packaging structure and its manufacturing process, which can solve the problems caused by the difference in thermal expansion coefficient between the wafer and the substrate.

Method used

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  • Wafer-class packaging technology and its chip structure
  • Wafer-class packaging technology and its chip structure
  • Wafer-class packaging technology and its chip structure

Examples

Experimental program
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Embodiment Construction

[0049]Please refer to FIG. 2 to FIG. 9 , which illustrate enlarged schematic diagrams of a wafer-level packaging manufacturing process according to a first preferred embodiment of the present invention. Please refer to Fig. 2 first, at first provide a wafer 210, wafer 210 is made up of a plurality of chips 211 (only one of them is shown in Fig. 2 ), wafer 210 has an active surface 212, and wafer 210 There are also a plurality of bonding pads 214 disposed on the active surface 212 of the wafer 210 . In addition, it is defined that the wafer 210 has an active side 213, the semiconductor device (not shown) and the pad 214 of the wafer 210 are located on the active side 213, and the outermost surface of the active side 213 of the wafer 210 is the active surface 212.

[0050] Then fabricate a reconfiguration circuit structure 220 on the active surface 212 of the wafer 210 (i.e., disposed on the active side of the wafer 210), and the reconfiguration circuit structure 220 has an ins...

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PUM

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Abstract

A chip structure at least includes a crystal circle, an insulating layer, a conductive ball, multi ball pads, a welded cover layer and multi welded balls. The chip possesses an active surface on which there is an insulating layer with multi openings perforating said layer. Conducting resin is filled into the openings, and the multi ball pads are positioned on the insulating layer, electrically connecting to said conducting resin. The welded cover layer covers on the insulating layer with multi ball pads being exposed. The welded ball is positioned on the ball pad.

Description

technical field [0001] The present invention relates to a wafer-level package, and in particular to a wafer-level package that can solve the problem of thermal expansion coefficient difference between a chip and a motherboard. technical background [0002] In today's information-explosive society, electronic products are ubiquitous in daily life. No matter in food, clothing, housing, transportation, entertainment, products composed of integrated circuit devices are used. With the continuous evolution of electronic technology, products with more complex functions and more user-friendly products are introduced. In terms of the appearance of electronic products, they are also designed towards the trend of light, thin, short and small. Therefore, in terms of semiconductor packaging technology, we have developed Many forms of high-density semiconductor packaging. The above-mentioned purpose can be achieved through Chip Scale Package technology. The cross-sectional size of the fi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/56H01L21/50H01L23/48
CPCH01L2224/16225H01L2224/73204H01L2224/32225H01L2924/00
Inventor 许志行
Owner VIA TECH INC