Over-all wiring method for standard units based on optimized time delay and key network techniques

Abstract

An over-all wiring method for standard units with optimized time delay includes creating over-all wiring diagram, configuring initial wiring tree with the shortest length, configuring key network composed of key pins, key sides and the weight, virtual source point and convergent point of each orientative side, reconfiguring the wiring tree from a group of sides with minimal division for reducing time delay, comparing the given delay data with optimized delay, and iterating to obtain wiring tree of over-all network.

Description

technical field [0001] A standard cell general wiring method based on key network technology to optimize time delay belongs to the field of computer aided design of integrated circuits, in particular to the field of standard cell general wiring. Background technique [0002] In the VLSI design of VLSI, the physical design is the main link in the VLSI design process. The related computer-aided design technology is called layout design, and the overall wiring has a great influence on the success of the final detailed wiring and the performance of the chip. At present, the manufacturing process of integrated circuits has entered the stage from deep submicron DSM to ultra-deep submicron VDSM, and the design scale of integrated circuits is also developing from ultra-large-scale VLSI, very large-scale ULSI to G-large-scale GSI. At this time, interconnection Line delay has surpassed gate delay to become the main factor affecting chip performance. Therefore, not only to optimize t...

AI Technical Summary

Problems solved by technology

Method (1) has a certain blindness in the allocation of delay constraints, and often the delay allocation results do not match the actual wiring requirements, making it impossible to improve the crowded line network

Method (2) uses the greedy trial method to determine the blindness of the line network that needs to improve the delay, and cannot realize active control

At the same time, the total number of critical paths is generally large, and all critical paths must be judged after redistribution of each line network, which greatly reduces the solution speed

Their common disadvantages are: the constraints on the intermediate routing results are relatively strict, which will have a greater impact on other optimization objectives of the overall routing such as routing congestion; their critical paths are static and cannot reflect the newly generated timeout of the circuit during the solution process Happening

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