One-shot signal generating circuit

Abstract

A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by signal PG and whose end instant is determined by signal DST.

Description

technical field [0001] The present invention relates to a one-shot signal generating circuit for generating a one-shot signal for determining the internal operation timing of an asynchronous memory. Background technique [0002] Conventional asynchronous memories operate by generating a one-shot signal internally when an external address changes. As a one-shot signal generating circuit for generating the above-mentioned one-shot signal, generally use such as Figure 19 the circuit described. The one-shot signal generating circuit shown in the figure detects changes (transitions) of address signals A0 to AX as input signals, generates a plurality of pulse-shaped address transition detection signals (hereinafter referred to as ATD signals), and then transfers the above-mentioned plurality of The ATD signal is synthesized into a one-shot signal. Based on the one-shot signal generated above, various internal signals for providing timing of internal operations, such as a latch ...

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Problems solved by technology

Therefore, according to this circuit method, the delay time of the series-connected NOT gates is easily affected by manufacturing variation, and it is difficult to obtain an accurate delay time.

[0017] (3) Splitting of the pulse signal due to the time lag of the input signal

[0018] When the delay time of the delay circuit 170 constituting each address transition detection circuit is shortened due to a change in the current drive capability of the transistor, there will be a case where the input signal cannot be transferred from the address through the NOR gate 6 depending on the degree of time lag of the input signal. The ATD signals output by each address transition detection circuit are synthesized into one pulse signal, and multiple pulse signals are output from NOR gate 6

Therefore, if the pulse signal output from the NOR gate circuit 6 is divided into a plurality, an accurate one-shot signal cannot be generated.

[0019] (4) Changes in pulse width due to shortening of the period of the input signal

Thus, according to Figure 19 In the configuration shown, there is a problem that when the period of the address signal becomes shorter, the pulse width becomes shorter.

[0024] (5) Changes in the pulse width due to the input signal of the trigger pulse

As a result, the pulse width of signal S175 is shorter than that required by the normal

[0027] As mentioned above, since the above-mentioned background art adopts such a configuration that the pulse width of the one-shot signal is specified using a delay circuit, the pulse width of the one-shot signal is susceptible to changes in the delay time of the delay circuit, time lag of the input signal, input One-shot signals cannot be generated stably due to the influence of periodic changes in the signal, trigger pulses occurring on the input signal, etc.

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