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Packaging component for semiconductor chip

A packaging and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as limited use range, reduce manufacturing steps, improve product electrical performance, and improve the use of space.

Inactive Publication Date: 2003-07-09
SILICON INTEGRATED SYSTEMS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this patent can only use die-level capacitors, and its capacitance value is only about a few hundred pico Farads (picoFarad), which is quite limited in comparison.

Method used

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  • Packaging component for semiconductor chip
  • Packaging component for semiconductor chip
  • Packaging component for semiconductor chip

Examples

Experimental program
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Embodiment Construction

[0032] Structural features of the present invention are described in detail as follows in conjunction with accompanying drawing and embodiment:

[0033] As shown in FIG. 3 , it is a perspective schematic diagram of a first embodiment of a semiconductor chip package of the present invention, wherein the package 30 includes a substrate 36 , a chip 32 and several capacitors 31 embedded on the chip 32 . The substrate 36 is used as a carrier for the chip 32 , which can be used in a ball array package or equivalently replaced by a leadframe, which is not limited in the present invention. The several capacitors 31 are fixed on the power line (V dd )33(25) and ground wire (V ss ) between 34. In other words, the external capacitors in the prior art are placed outside the chip 32 and are electrically connected to the power line 33 and the ground line 34 through the input and output pads. Therefore, the overall conduction path is long, resulting in a voltage drop. On the contrary, the...

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PUM

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Abstract

The present invention relates to a package of semiconductor chip, including a substrate and a chip placed on the substrate. On the chip at least a power supply wire and a grounding wire are set, and on the surface of the chip at least a capacitor is set, said capacitor is electrically connected to power supply wire and grounding wire, and the capacity of the capacitor is above microfared level, said capacitor is fixed on the surface of the chip by using conductive adhesive or using tin soldering. Its conduction path is short, so that it can prevent voltage drop, and can effectively filter noise signal.

Description

(1) Technical field [0001] The invention relates to a semiconductor chip, in particular to a semiconductor chip package with capacitors embedded on the surface of the chip, so as to improve the electrical performance of the semiconductor chip. (2) Background technology [0002] With the development of semiconductor process technology, hundreds of thousands or even millions of transistors are often built in an integrated circuit. If these transistors are in working state at the same time, such as being turned on or off at the same time, it will cause instantaneous pulse effect and noise to the power supply, which will make the operation result of the integrated circuit in an uncertain state. [0003] In order to solve the voltage regulation and noise problems of the power supply, the existing method is to add several capacitors on the circuit board connected to the integrated circuit. Such as figure 1 As shown, it is a perspective view of the plastic ball array package. The...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/00H01L23/12H01L23/58
CPCH01L2924/0002
Inventor 林蔚峰吴明园吴忠儒
Owner SILICON INTEGRATED SYSTEMS
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