Packaging component for semiconductor chip
A packaging and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as limited use range, reduce manufacturing steps, improve product electrical performance, and improve the use of space.
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[0032] Structural features of the present invention are described in detail as follows in conjunction with accompanying drawing and embodiment:
[0033] As shown in FIG. 3 , it is a perspective schematic diagram of a first embodiment of a semiconductor chip package of the present invention, wherein the package 30 includes a substrate 36 , a chip 32 and several capacitors 31 embedded on the chip 32 . The substrate 36 is used as a carrier for the chip 32 , which can be used in a ball array package or equivalently replaced by a leadframe, which is not limited in the present invention. The several capacitors 31 are fixed on the power line (V dd )33(25) and ground wire (V ss ) between 34. In other words, the external capacitors in the prior art are placed outside the chip 32 and are electrically connected to the power line 33 and the ground line 34 through the input and output pads. Therefore, the overall conduction path is long, resulting in a voltage drop. On the contrary, the...
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