Method for preparation of read-only memory
A technology of read-only memory and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., which can solve the problems of time-consuming manufacturing and difficult improvement of defects, and achieve the effect of simplifying the process
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no. 1 example
[0051] Figure 1A to Figure 1E It is a sectional view of the manufacturing process of the mask ROM according to the first embodiment of the present invention. Figure 2A to Figure 2E for Figure 1A to Figure 1E A top view of the memory cell area. Among them, Figure 1A to Figure 1E The storage unit area is Figure 2A to Figure 2E The section view along the line I-I' in .
[0052] Please refer to Figure 1A with Figure 2A Firstly, a substrate 100 is provided, and the substrate 100 can be divided into a memory cell area 102 and a peripheral circuit area 104 , wherein a memory cell array 106 has been formed in the memory cell area 104 , and a plurality of transistors 108 have been formed in the peripheral circuit area 104 .
[0053] The memory cell array 106 in the memory cell area 102 is composed of a plurality of gates 106a, a plurality of bit lines 106b and a plurality of word lines 106c. Wherein, the gate 106a is located on the base 100, and a gate dielectric layer 106d is...
no. 2 example
[0065] Figure 3A to Figure 3E It is a sectional view of the manufacturing process of the mask ROM according to the second embodiment of the present invention. Figure 4A to Figure 4E for Figure 3A to Figure 3E A top view of the memory cell area. in, Figure 3A to Figure 3E The storage unit area is Figure 4A to Figure 4E The sectional view along the line II-II'. In the second embodiment, the same components as those of the first embodiment are given the same symbols and their descriptions are omitted.
[0066] Please refer to Figure 3A and Figure 4A Firstly, a substrate 100 is provided, and the substrate 100 can be divided into a memory cell area 102 and a peripheral circuit area 104 . A memory cell array 106 has been formed in the memory cell area 104 , and a plurality of transistors 108 have been formed in the peripheral circuit area 104 . The structures of the memory cell array 106 and the transistor 108 are the same as those of the first embodiment, and will no...
no. 3 example
[0077] 5A to 5D are cross-sectional views of the manufacturing process of the mask ROM according to the third embodiment of the present invention. Figure 6A to Figure 6D It is a top view of the memory cell region in FIG. 5A to FIG. 5D . Wherein, the memory cell area of Fig. 5A to Fig. 5D is Figure 6A to Figure 6D Sectional view along the line III-III'. In the third embodiment, the same components as those in the first embodiment are given the same symbols and their descriptions are omitted.
[0078] Please refer to Figure 5A with Figure 6AFirstly, a substrate 100 is provided, and the substrate 100 can be divided into a memory cell area 102 and a peripheral circuit area 104 . A memory cell array 106 has been formed in the memory cell area 102 , and a plurality of transistors 108 have been formed in the peripheral circuit area 104 . The structures of the memory cell array 106 and the transistor 108 are the same as those of the first embodiment, and will not be repeated ...
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