Embedded capacitor structure used for logic integrated cireuit

Abstract

A process for preparing the vertical 3D MIM capacitor structure features that a vertical 3D MIM capacitor structure compatible with the inlaid copper structure is made on base material to decrease the area of the capacitor structure in logic circuit and increase the capacitance density of the capacitors. A process for preparing an inlaid copper structure in IC in order to decrease the number of masks used in preparing said capacitor structure is also disclosed.

Description

(1) Technical field [0001] The present invention relates to a vertical three-dimensional metal-insulated metal capacitor structure, in particular to a method for manufacturing a vertical three-dimensional metal-insulated metal capacitor structure that integrates a copper inlay process and is compatible with the copper inlay process in a logic integrated circuit. (2) Background technology [0002] Precision capacitors for complementary metal oxide semiconductor (CMOS, complementary metal oxide semiconductor) analog applications are generally metal-insulated metal capacitors (MIM capacitor structure, metal-insulator-metal capacitor) or polysilicon-insulated polysilicon capacitors (PIP capacitor, polysilicon-insulator -polysilicon capacitor). [0003] However, polysilicon-insulator-polysilicon capacitors are less used due to many problems in CMOS applications. In particular, polysilicon-insulator polysilicon capacitors are generally implemented before CMOS, and heating and oxi...

AI Technical Summary

Problems solved by technology

In addition, the traditional planar capacitor structure requires three additional photomasks to respectively form the lower electrode plate 104, the dielectric layer 106 and the upper electrode plate 108, and the planar capacitor process is difficult to be compatible with the copper damascene process

Images