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Surface installation chip package

A surface mount, chip packaging technology, applied in measuring devices, electrical devices, instruments, etc., can solve cumbersome problems

Inactive Publication Date: 2004-07-07
YAMAHA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This requires very tedious work to prepare a special image processing program and a special image pickup device for needle testing

Method used

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  • Surface installation chip package
  • Surface installation chip package
  • Surface installation chip package

Examples

Experimental program
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Effect test

no. 1 example

[0026] figure 1 The appearance of a predetermined surface (or back surface) of the chip-scale package 100 according to the first embodiment of the present invention is shown. Here, the chip size package 100 may correspond to a surface mount chip package, and it may independently hold two hundred "square" semiconductor chips 200 therein. Each individual semiconductor chip 200 has an integrated circuit (not shown) formed on its main surface, and is covered with a molding resin (or molding resin) forming the package case 110 . Incidentally, the molding resin is formed so as to avoid a copper post used as a mark, which will be described below. That is, copper posts used as markers and other copper posts used as conductors are embedded in molding resin.

[0027] The solder balls 120 constituting the external electrodes are formed on one surface of the package 110 matching the main surface of the semiconductor chip 200 (in other words, the outer surface of the package case 100 co...

no. 2 example

[0041] In the first embodiment, the polished surface of the copper post 140A is directly used for the marker 130, whereby the copper post 140A is exposed to the outside atmosphere and will be easily damaged due to oxidation, which will affect the reliability of manufacturing. In order to avoid this drawback, the second embodiment such as Figure 5 Constructed as shown, a solder layer 160 is formed again on the polished surface of the copper post 140A, and this solder layer is used as a discrimination element of the marker 130 .

[0042] As above, the size of the copper post 140A is larger than that of the copper post 140B, whereby the square cross-sectional area of ​​the copper post 140A becomes larger than the circular cross-sectional area of ​​the copper post 140B. The solder layer 160 is made of the same material as the solder ball 120 serving as an external electrode, wherein the material is heat-treated to form the solder layer 160 in a predetermined shape and size. As d...

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Abstract

A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.

Description

technical field [0001] The present invention relates to surface mount chip packaging, such as chip scale packaging (or chip scale packaging, ie CSP), in which semiconductor chips are probing tested under precise positioning using test setups. [0002] This application claims priority from Japanese Patent Application No. 2002-370205, the contents of which are incorporated herein by reference. Background technique [0003] As is well known, a chip-scale package is a surface-mounted chip package used to secure a semiconductor chip at a predetermined position; their size is substantially equal to that of a semiconductor chip, making them ideal for achieving a combination of size and weight reductions in electronic devices. Packaging technology has received extensive attention. When a semiconductor chip is mounted on a chip size package, pin testing is required after the dicing process in order to improve the defect detection rate in the manufacturing stage. Probe testing is pe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/12H01L21/66H01L23/31H01L23/544
CPCH01L2223/5442H01L2223/5448H01L2224/13023H01L2223/54426H01L23/544H01L2223/54473H01L23/3114H01L24/05H01L24/06H01L24/13H01L2224/023H01L2224/05001H01L2224/05008H01L2224/05026H01L2224/05569H01L2224/05571H01L2224/06135H01L2224/05647H01L2924/00014H01L2224/05124H01L2224/05147H01L2924/0001H01L22/00
Inventor 大仓喜洋
Owner YAMAHA CORP
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