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Improved phase/frequency detector and phase lock loop circuit

A frequency detector and detector technology, applied in the direction of electrical components, automatic power control, oscillating tubes, etc., can solve problems such as increasing costs

Inactive Publication Date: 2004-10-20
WOLFSON MICROELECTRONICS LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, complex state machines can add significant cost

Method used

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  • Improved phase/frequency detector and phase lock loop circuit
  • Improved phase/frequency detector and phase lock loop circuit
  • Improved phase/frequency detector and phase lock loop circuit

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Embodiment Construction

[0057] Figure 4 A PLL lock detector 1 is shown comprising a cycle slip detector 2 and a timer circuit 5 according to one embodiment. The cycle slip detector 2 includes a phase and frequency detector (PFD) and a NAND gate (NAND) 3, wherein the phase and frequency detector has two input terminals or PFD blocking devices F1 and F2, these two input terminals or PFD The locking means F1 and F2 are respectively connected to a reference clock signal (REF) and a derived clock signal (DER) as output by a voltage controlled oscillator (VCO). The outputs of the input block F1 and F2 are connected to the UP and DOWN cycle slip detector circuits (CSD(U) and CSD(D)), respectively, which circuits include delay elements D1 or D2 and output or cycle slip block devices F3 or F4. The CK input of each output latch F3 and F4 is connected to the corresponding clock input (reference or corresponding derived).

[0058] The reference clock is connected to the CK input of PFD lock F1, while the der...

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Abstract

The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.

Description

technical field [0001] The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and lock detectors for phase locked loop (PLL) circuits. Background technique [0002] A phase-locked loop (PLL) is a well-known circuit for locking a locally occurring signal, such as a clock signal, to an external or reference signal. This circuit can be used in telecommunication receiver equipment or digital audio equipment, where these devices receive a reference signal and need to generate a local clock signal, the frequency and phase of which are related to the received reference signal (as a condition for locking), so that correct Receive the incoming information signal. figure 1 A schematic structure of a PLL is shown, which includes: a phase and frequency detector (PFD), a charge pump (CP), a loop filter (LF) and an oscillator (VCO) in a feedback loop. The detector (PFD) detects the frequency or phase difference between the signal output by the osci...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/089H03L7/095H03L7/10
CPCY10S331/02H03L7/10H03L7/0891H03L7/095H03L7/101
Inventor 莱索保罗
Owner WOLFSON MICROELECTRONICS LTD