Semiconductor memory device with static memory cells

Abstract

A semiconductor memory device, comprises memory cell storing data; and word line and pair of bit lines connected to memory cell. The memory cell includes first inverter including first load element and first driving element having N channel metal oxide semiconductor (MOS) transistor; and second inverter cross-coupled with first inverter, including a second load element and a second driving element having another N channel MOS transistor. - A semiconductor memory device, comprises a memory cell storing data; and a word line and a pair of bit lines connected to the memory cell. The memory cell includes: - (1) a first inverter including a first load element and a first driving element having an N channel metal oxide semiconductor (MOS) transistor; - (2) a second inverter cross-coupled with the first inverter, including a second load element and a second driving element having another N channel MOS transistor; - (3) first and second storage nodes connected respectively to output nodes of the first and second inverters; - (4) first and second gate elements each including a P channel MOS transistor having a gate electrode (218, 220) connected to the word line, connecting the first and second storage nodes to one bit line and the other bit line of the pair of bit lines, respectively; - (5) a first metal interconnection (276) forming the first storage node and provided stacked on the first driving element and the first gate element formed on a substrate surface; and - (6) a second metal interconnection forming the second storage node and provided stacked on the second driving element and the second gate element formed on the substrate surface. - The first and second load elements are provided above the first and second metal interconnections.

Description

technical field [0001] The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory including a static memory cell. Background technique [0002] SRAM (Static Random Access Memory), which is a typical type of semiconductor memory, is a RAM that does not require a refresh operation to hold stored data. The memory cell of the SRAM has a structure in which a flip-flop that cross-connects two inverters consisting of a load element and a drive transistor is connected to a pair of bit lines via an access transistor. [0003] As a typical memory cell in SRAM, a CMOS type memory cell in which a P-channel MOS transistor constitutes a load element and an N-channel MOS transistor constitutes a drive transistor and an access transistor is generally known. This CMOS type memory cell has low power consumption, and in terms of CMOS characteristics, it has excellent static noise margin (hereinafter, also referred to as "SNM") characteristics, an...

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Problems solved by technology

[0010] However, if the reduction in voltage continues to progress, even the above-mentioned conventional CMOS memory cells cannot cope with it.

That is, this is because, in this CMOS memory cell, the potential of the storage node is further lowered than the power supply potential, which is a low potential, due to the threshold voltage of the access transistor constituted by an N-channel MOS transistor. cannot turn on the drive transistor

[0011] Here, lowering the threshold voltage of the N-channel MOS transistor is also considered, but the lowering of the threshold voltage leads to an increase in leakage current, which in turn increases power consumption

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