Array type reconstructural DSP engine chip structure based on CORDIC unit

A chip structure, array technology, applied in the field of DSP, can solve the problem of fixed chip data word width

Inactive Publication Date: 2005-01-12
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In order to solve the problem of fixed data word width of the existing coarse-grained DSP array chips, an array type reco...

Method used

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  • Array type reconstructural DSP engine chip structure based on CORDIC unit
  • Array type reconstructural DSP engine chip structure based on CORDIC unit
  • Array type reconstructural DSP engine chip structure based on CORDIC unit

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specific Embodiment approach 1

[0005] Specific implementation mode one: the following combination figure 1 , Figure 3 to Figure 6 This embodiment will be specifically described. An interconnection bus 2 is arranged between several reconfigurable processing units 1 arranged in an array, and the vertical interconnection bus 2-1 and the horizontal interconnection bus 2-2 are connected to each other through a reconfigurable switch network 3. Each adjacent reconfigurable processing unit 1 in the vertical arrangement direction is vertically connected through the basic unit data line 4, and the basic unit data line 4 is connected with the horizontal interconnection bus 2-2 through the reconfigurable switch network 3, The reconfigurable processing unit 1 is a several-stage pipeline structure of the cordic algorithm, the adder and the adder in the corresponding position in the same pipeline of the horizontally adjacent reconfigurable processing unit 1, the shifter and the shifter in the corresponding position The...

specific Embodiment approach 2

[0009] Specific implementation mode two: the following combination figure 1 and figure 2 This embodiment will be specifically described. The difference between this embodiment and Embodiment 1 is: the interconnection bus 2 is a 64-bit interconnection bus, the reconfigurable switch network 3 is composed of several switch tubes 3-1, and the switch tubes 3-1 are arranged vertically At the intersection of the 64 interconnection buses 2-1 and the 64 horizontal interconnection buses 2-2, the two main working poles of the switch tube 3-1 are connected to the longitudinal interconnection bus 2-1 and the horizontal interconnection bus 2-1 respectively. Connected to the bus 2-2, the control pole of the switch tube 3-1 is connected to the preset memory 3-2 for controlling the switch tube. When this embodiment is working, the configuration of the chip is determined by setting whether the switch tube 3-1 is connected or turned off in the preset memory 3-2 through programming. The switc...

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Abstract

Interconnection bus including longitudinal interconnection bus and transverse interconnection bus interconnected through reconfigurable switch network are setup between reconfigurable processing units arranged in array. Reconfigurable processing units are connected to each other longitudinally through basic unit data lines, which are connected to transverse interconnection bus through reconfigurable switch network. In transverse adjacent reconfigurable processing units at same stage of pipeline, their adders, shifters, accumulators, and register are connected through interconnection lines containing control switch. Reconfigurable processing unit itself of using COROIC algorithm possesses high reconfigurability, providing features of realizing wide used DSP algorithms, simple structure and rules, easy of modularized. Thus, the reconfigurable processing unit is suitable for being as core unit in reconfigurable chip.

Description

Technical field: [0001] The invention relates to a reconfigurable (hardware programmable) array chip internal structure composed of coarse-grained basic units with a CORDIC algorithm as the core, and the structure is mainly used in the DSP field. Through the configuration of the hardware reconfigurable resources in the chip, it can efficiently execute the core links in most DSP algorithms, and can be used as the acceleration engine in the DSP system. Background technique: [0002] CORDIC (COordinate Rotation DIgital Computing), also known as coordinate rotation digital calculation method, is an iterative method for calculating generalized vector rotation. By setting the few parameters in the CORDIC unit, it can implement a variety of basic functions and operations with simple "shift-add" iterations, such as: trigonometric functions, inverse trigonometric functions, hyperbolic functions, inverse hyperbolic functions Functions, logarithmic operations, exponential operations, ...

Claims

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Application Information

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IPC IPC(8): G06F7/48
Inventor 杨宇毛志刚
Owner HARBIN INST OF TECH
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