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Semiconductor device and methods of manufacture

A technology of semiconductors and transistors, applied in the field of complementary field effect transistors and its manufacturing, can solve the problems of reduced mobility, reduced hole mobility, and difficulty in achieving

Active Publication Date: 2005-07-27
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, uniaxial tensile strain reduces hole mobility, while uniaxial compressive strain reduces electron mobility
Ge ion implantation can be used to selectively induce strain relaxation without reducing the mobility of holes or electrons, but this is difficult to achieve due to the close proximity of N-channel transistors to P-channel transistors.

Method used

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  • Semiconductor device and methods of manufacture
  • Semiconductor device and methods of manufacture
  • Semiconductor device and methods of manufacture

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Embodiment Construction

[0046] In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, together with the accompanying drawings, as follows:

[0047] Figure 1A-1E It is a series of cross-sectional views showing the steps of a method for forming a semiconductor device according to a preferred embodiment of the present invention, which is to form a transistor with a strained channel region in a semiconductor wafer. The steps and semiconductor devices of the present invention shown here can be applied in different circuits. For example, the embodiments of the present invention can be applied to NOR gates, logic gates, inverters, exclusive OR gates (XOR gates), NAND gates, A circuit such as a PMOS transistor as a pull-up transistor and an NMOS transistor as a pull-down transistor.

[0048] Please refer to Figure 1A , shows a wafer 100 having a first transistor 102 and a second transistor 104...

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Abstract

The present invention discloses a semiconductor device and a method of manufacture, the semiconductor device utilizes a substrate having a surface layer with a <100> crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source / drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like. The present invention effectively improve the efficiency of the transistor.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a complementary field-effect transistor and a manufacturing method thereof. Background technique [0002] The size reduction of metal-oxide-semiconductor field-effect transistors (MOSFET), including the reduction of gate length and gate oxide size, has promoted the speed and performance per unit element of integrated circuits in the past few decades. , density and cost improvements. In order to further enhance the performance of the transistor, the channel region can be strained to improve the mobility of carriers. Generally speaking, it is better to apply tensile stress to the N-type channel region of the NMOS (N-type metal oxide semiconductor) transistor along the source-drain direction, and to apply tensile stress along the direction of the PMOS (P-type metal oxide semiconductor) transistor. The source-drain orientation exerts compressive stress on its P-type channel region....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/76H01L21/8238H01L27/092H01L29/78H01L31/0328
CPCH01L21/823814H01L29/7833H01L29/7843H01L29/665H01L29/6659H01L21/823864H01L29/7845H01L21/823807H01L29/045H01L29/6656
Inventor 黄健朝杨富量甘万达胡正明葛崇祜李文钦柯志欣
Owner TAIWAN SEMICON MFG CO LTD