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Semiconductor manufacturing method and an exposure mask

A manufacturing method and semiconductor technology, applied in the field of exposure masks, can solve the problem of no correction pattern 106, etc., and achieve the effect of suppressing the shortening phenomenon

Inactive Publication Date: 2006-01-04
FUJITSU MICROELECTRONICS LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] exist Figure 2B In the shown method, when the wiring patterns 105 are arranged close to each other, there is not enough space to accommodate the required correction pattern 106, especially in the circular area B, resulting in the same Figure 2A The same problem as shown in

Method used

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  • Semiconductor manufacturing method and an exposure mask
  • Semiconductor manufacturing method and an exposure mask
  • Semiconductor manufacturing method and an exposure mask

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0043] A mask pattern according to a first embodiment of the present invention will be described below.

[0044] Figure 4 is a plan view of a mask pattern according to a first embodiment of the present invention. Figure 4 The mask pattern shown in is, for example, a mask pattern of an exposure mask used in forming a wiring layer on a semiconductor device.

[0045] see Figure 4 , the mask pattern 10 includes a wiring pattern 11 and an auxiliary pattern 12 formed within the wiring pattern 11 . Four rectangular patterns 11 are placed in parallel, and one rectangular pattern 11 is placed perpendicular to the four patterns. The ultraviolet light is shielded from the wiring pattern 11 and transmitted through the wiring pattern 11 .

[0046] The auxiliary pattern 12 is formed inside the wiring pattern 11, and is configured to shield violet light. Each wiring pattern 11 has a first region 11-1 at its longitudinal end 11a, and has a second region 11-2 between these first region...

no. 1 example

[0056] Using the exposure mask according to the first embodiment of the present invention, a wiring pattern is formed on a resist film coated on a silicon substrate.

[0057] Figure 5A A mask pattern is shown, which has auxiliary patterns and wiring patterns formed according to the first embodiment. Figure 5b shows a prior art mask pattern for comparison, with hammerheads and wiring patterns.

[0058] see Figure 5A , the mask pattern according to the first embodiment includes a wiring pattern 11 and an auxiliary pattern 12 placed inside the wiring pattern 11 . The reduced longitudinal length L2 of the wiring pattern 11 projected onto the resist film is 750 nm. The reduced width of the wiring pattern 11 projected onto the resist film was 90 nm. The reduced longitudinal length of the auxiliary pattern 12 is 650 nm. The reduced width W3 of the auxiliary pattern 12 is in the range of 4nm˜15nm. The distance L1 between the end portion 11 a of the wiring pattern 11 and the en...

no. 2 example

[0090] A method for manufacturing a semiconductor device according to a second embodiment of the present invention will now be described. The photolithography process in the semiconductor device manufacturing method according to this embodiment uses an exposure mask having the mask pattern according to the first embodiment described above.

[0091] Figures 11A-11C Photolithographic steps for manufacturing a semiconductor device according to a second embodiment of the present invention in which a gate layer is formed on a silicon substrate as a gate will be described.

[0092] exist Figure 11A In the shown steps, a gate oxide film 71 and a polysilicon film 72 are formed on a silicon substrate 70 . And on the surfaces of these films, a positive type resist film 73 is formed, and then prebaked to remove the solvent from the resist film 73 .

[0093] exist Figure 11A In the illustrated steps, an exposure mask 74 having an exposure mask pattern 74b is used for the exposure p...

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Abstract

A semiconductor manufacturing method is disclosed. The method includes a lithography process having an exposure step for projecting an image of a mask pattern of a mask onto a photo resist layer using exposure light. The mask pattern includes a first pattern having a light transparency characteristic corresponding to a circuit pattern, and a second pattern having an inverted light transparency characteristic arranged within and spaced apart from the first pattern.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing method and an exposure mask used in a lithography process for manufacturing a semiconductor device. Background technique [0002] Since MOS type logic devices require higher functionality and memory devices require greater storage capacity, the degree of integration of semiconductor devices is constantly increasing by four times every three years. The increase in integration is achieved by miniaturizing the design size of semiconductor devices. This miniaturization is very advantageous because it increases operating speed and reduces power consumption in semiconductor devices, and thus is increasingly demanded. [0003] Under such circumstances, scaling down to a size of 0.1 μm or less has been required as the minimum process size of semiconductor devices, such as wiring pitch, gate gap, etc., and the manufacturing process of semiconductor devices has become increasingly difficult. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027G03F7/00G03F1/36G03F1/68G03F7/20
CPCG03F1/144G03F1/36G03F7/70441G03F7/70433H01L21/0274
Inventor 杉本文利
Owner FUJITSU MICROELECTRONICS LTD