Electronic data memory device for a high read current

Abstract

The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100). The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303), the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408 a , 408 b) are arranged at opposite lateral areas of the fin (405), a third gate element (408 c) being arranged in an area of the fin (405) that is parallel to the surface of the substrate (401).

Description

technical field [0001] Generally, the present invention relates to memory devices for data storage which can be miniaturized and integrated on a substrate. In particular, the present invention relates to a DRAM memory cell (DRAM dynamic random access memory) having a storage capacitor and a selection capacitor connected to the storage capacitor. The data is stored in the form of charging the energy storage capacitor, and the "0" and "1" of the storage state are determined according to the positive and negative poles charged by the energy storage capacitor. Background technique [0002] The storage capacitor is written or read by addressing the select transistor. The charge stored in the storage capacitor is recombined according to the leakage current through the selection transistor, etc. In this way, the charge must be renewed at a predetermined refresh cycle. This update period is typically 64 milliseconds (ms). [0003] In particular, the present invention relates to a...

AI Technical Summary

Problems solved by technology

The disadvantage of this design in which the width of the channel layer (fin width) is proportional to the length of the channel layer (fin depth) is that while obtaining sublithographic feature dimensions, there are strict requirements for lithographic technology

[0013] A fatal disadvantage of known memory devices using FinFETs is the high processing technology expense required to fabricate said fins.

This increases the manufacturing cost of the entire memory device

Also, it is difficult to manufacture such small structures with small production fluctuations

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