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Multiport memory

A memory and multi-port technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of increased power consumption and increased circuit scale

Inactive Publication Date: 2006-03-01
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, for a circuit having a low access capability, the circuit scale increases undesirably, and the power consumption also further increases

Method used

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Examples

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specific example 1

[0064] figure 1 is a block diagram showing the structure of the multi-port memory in the specific example 1 which is a specific example of the present invention. figure 2 and 3 Both are block diagrams showing the internal structure of memory cells in the multi-port memory.

[0065] exist figure 1 , reference numeral 101 denotes a CPU (Central Processing Unit). Reference numeral 102 denotes a row decoder. Reference numeral 103 denotes a memory cell, and the memory cells 103 are arranged in an array form in the direction of rows and columns. Reference numeral 104 denotes a read / write capability adjustment circuit.

[0066] exist figure 2 Among them, reference numeral 201-1 to reference numeral 201-m denote writing circuits of m units (m is an integer not less than 1). Reference numeral 202 denotes a memory hold circuit. Reference numerals 203-1 to 203-n denote read circuits of n units (n is an integer not less than 1). Each of the memory cells has a read / write capab...

specific example 2

[0085] exist figure 1 In the shown structure, a plurality of write circuits 201 - i and a plurality of read circuits 203 - j are provided in each memory cell 103 . However, some memory cells 103 are configured to include at least one single write circuit or one single read circuit.

[0086] Between the wirings of these circuits, interference due to the close state of the wirings such as crosstalk may occur and generate noise. As an example, in a structure in which an arbitrary first bit line BL-1 and an arbitrary second bit line BL-2 are adjacent to each other, when the bit line BL-1 is operating, noise due to interference may cause the circuit to become non-operating . Therefore, when the amount of noise of the device as a whole has been determined to be large, it is preferable not to perform operations related to the first bit line while the second bit line adjacent to the first bit line is operating.

[0087] In specific example 2 of the present invention, such as Fig...

specific example 3

[0093] exist figure 1 In the configuration shown, each of the write and read circuits can operate at different rates. Such as Figure 11 and 12 As shown, in Example 3 of the present invention, an operation completion determination circuit 106 is provided for each circuit. requires attention, Figure 11 The structure in corresponds to figure 2 in the structure, Figure 12 The structure in corresponds to image 3 in the structure. In this example, the run completion detection circuit 106 detects the completion of a write operation or a read operation. Depending on the detection of completion, the next access (write operation, read operation) is performed. The completion determination circuit 106 operating in the above-mentioned manner serves as an operation state determination circuit for determining the number of times of writing or the number of reads per unit time according to the operation state of each circuit.

[0094] Figure 13 A timing chart in the case wher...

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PUM

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Abstract

This multiport memory has a memory hold circuit, a plurality of write circuits and read circuits, and a read / write capability regulating circuit. The read / write capability regulating circuit individually sets a write / read capability of each of the write / read circuits. The read / write capability regulating circuit determines, using an operating state determining circuit, the number of writing / reading times per unit time in accordance with an operating state of each of the read / write circuits. As the operating state determining circuit used is a noise amount detection circuit, an operation completion detecting circuit, or a potential fluctuation detecting circuit.

Description

technical field [0001] The present invention relates to a multi-port memory having a memory holding circuit and a plurality of writing circuits or a multi-port memory having a memory holding circuit and a plurality of reading circuits on a semiconductor substrate. The present invention is particularly preferably suitable for the case where the storage and holding circuit is a register file, SRAM (Static Random Access Memory), or the like. Background technique [0002] As is well known, as a commonly used multi-port memory, the memory performs not only one write or read per unit time, but multiple times to obtain a higher write / read capability than the per unit time determined by the bit width of each circuit. strong ability. "A Media Processor-Oriented Multiplex Octal-Port SRAM Operating at 350 MHz with a Variable Word-Size Multiplier, Ichida, Sakurai et al., Shingku Giho April 96 (pp. 59-60, Figure 6 )" discloses an example of such a multi-port memory. [0003] In the co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/419G11C7/00
CPCG11C8/16G11C7/1075
Inventor 池田雄一郎
Owner PANASONIC CORP
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