Method for forming electronic devices in multi-layer structure of substrate

Abstract

A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing layer conforms to that of the laterally extending first layer; and depositing a pattern of at least one additional layer onto the top-most non-planarizing layer, such that the lateral location of the additional layer is defined by the shape of the topographic profile of the non-planarizing layer, and whereby the additional layer is laterally aligned with the topographic profile in the first layer.

Description

technical field [0001] The present invention relates to electronic devices, particularly organic electronic devices, and methods of forming the devices. Background technique [0002] Recently, semiconducting conjugated polymer thin-film transistors (TFTs) have been investigated for inexpensive logic circuits integrated on plastic substrates (C. Drury et al., APL 73, 108 (1998)) and high-resolution active-matrix Optoelectronic integrated devices and pixel transistor switches in displays (H. Sirringhaus et al., Science 280, 1741 (1998), A. Dodabalapur et al., Appl. Phys. Lett. 73, 142 (1998)). High performance TFTs have been demonstrated in test device configurations with polymer semiconductor and inorganic metal electrodes and gate dielectric layers. Carrier mobility as high as 0.1 cm2 / Vs and ON-OFF (on-off) current ratio of 106-108 have been achieved, which are comparable to the performance of amorphous silicon TFTs (H. Sirringhaus et al., Advance in Solid State Physics 39...

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Problems solved by technology

Furthermore, the positional accuracy of drop placement in techniques such as direct inkjet printing is often insufficient to obtain small overlapping capacitances

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