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Split network processor control information cache memory

A technology for caching and controlling information, used in the computer field

Inactive Publication Date: 2006-08-02
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, caches designed according to common applications obviously cannot achieve ideal results in network processors.

Method used

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  • Split network processor control information cache memory
  • Split network processor control information cache memory
  • Split network processor control information cache memory

Examples

Experimental program
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Embodiment Construction

[0123] The present invention is called split network processor control information cache memory (Split Control Cache, referred to as SCC). where it is applied such as figure 1 shown. For the sake of illustration, figure 1 Only the network processor structure of a single processing unit is shown. The processing unit consists of a processing core that performs calculations and an SCC that provides control information. In addition to the processing unit, there are a group of co-processors and several hardware functional units in the network processor, which are used to complete functions such as flow classification, checksum calculation, and flow management. The storage and movement of data packets in the off-chip data packet buffer memory is completed by the input / output interface and the data packet buffer controller. The data packet fields required for processing are also extracted by the data packet buffer controller and sent to the processing unit. The storage space tha...

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Abstract

This invention relates to split network processor controlling information high-speed buffer memory. It concludes: address identifier, which specifies the application correlated data or flow correlated data; App-Cache, which buffer stores application correlated data; Flow-Cache, which buffer stores flow correlated data; memory dispatcher, which dispatches the controlling information memory access requests coming from App-Cache and Flow-Cache. Flow-Cache is arranged with two work stacks so that when the processing element is using flow correlated data of one work stack to process data packet, the other work stack can read-in related flow correlated data to the next data packet by use of controlling information expected address coming from flow classifier. If the flow correlated controlling information is modified by processing element, when replacement takes place, the modified part should be written back to controlling information memory.

Description

technical field [0001] The invention is a mechanism for caching control information in message processing, which can be applied to high-speed and complex message processing in the Internet, and belongs to the field of computer technology. Background technique [0002] The network processor is a kind of special-purpose processor, which is usually used for flexible and high-speed data packet processing. It combines the advantages of ASIC and general-purpose CPU, and has the advantages of shortening the development cycle of routers and prolonging the lifetime of network equipment. Some manufacturers have launched various network processor products one after another. In order to achieve the intended purpose, these products usually adopt many new technologies in the ascendant. For example, the most common approach is to integrate multiple processing units on the same network processor, and use a dedicated instruction set optimized for network applications. Another often-used t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L45/18
Inventor 刘祯刘斌
Owner TSINGHUA UNIV