Multi-level cell memory device and associated read method
A technology of flash memory and memory unit, which is applied in the direction of electrical components, static memory, read-only memory, etc., and can solve problems such as the difficulty of sensing amplifiers and the difficulty of sensing small differences in current
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[0021] Hereinafter, several exemplary embodiments of the present invention will be described with reference to the corresponding drawings. These figures are given as teaching examples. Rather, the actual scope of the invention is defined by the claims that follow.
[0022] The exemplary embodiments generally relate to a NOR flash memory device including multi-level cells. In theory, each of the multilevel cells can store a random number of bits. However, for simplicity of illustration, the multi-level cells described below are adapted to store 2 bits each.
[0023] FIG. 1 is a block diagram of a NOR flash memory device according to an embodiment of the present invention. Referring to FIG. 1, a NOR flash memory device 100 includes a memory cell 1a, a Y-gate circuit 2a, a sense amplifier 10a, a latch circuit 20a, a selection circuit 30a, a reference voltage generator 40a, and a controller 50a.
[0024] The memory cell 1a is a multi-level cell including: a drain, a source, a ...
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