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Multi-level cell memory device and associated read method

A technology of flash memory and memory unit, which is applied in the direction of electrical components, static memory, read-only memory, etc., and can solve problems such as the difficulty of sensing amplifiers and the difficulty of sensing small differences in current

Active Publication Date: 2006-08-23
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Unfortunately, it is extremely difficult to make each sense amplifier have the same characteristics
It is difficult to sense small differences in the current flowing through the channel of a NOR flash memory device due to the mismatch in the characteristics of the sense amplifiers

Method used

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  • Multi-level cell memory device and associated read method
  • Multi-level cell memory device and associated read method
  • Multi-level cell memory device and associated read method

Examples

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Embodiment Construction

[0021] Hereinafter, several exemplary embodiments of the present invention will be described with reference to the corresponding drawings. These figures are given as teaching examples. Rather, the actual scope of the invention is defined by the claims that follow.

[0022] The exemplary embodiments generally relate to a NOR flash memory device including multi-level cells. In theory, each of the multilevel cells can store a random number of bits. However, for simplicity of illustration, the multi-level cells described below are adapted to store 2 bits each.

[0023] FIG. 1 is a block diagram of a NOR flash memory device according to an embodiment of the present invention. Referring to FIG. 1, a NOR flash memory device 100 includes a memory cell 1a, a Y-gate circuit 2a, a sense amplifier 10a, a latch circuit 20a, a selection circuit 30a, a reference voltage generator 40a, and a controller 50a.

[0024] The memory cell 1a is a multi-level cell including: a drain, a source, a ...

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Abstract

A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.

Description

technical field [0001] Generally speaking, the present invention relates to a NOR (or not) flash memory device. More particularly, the present invention relates to a NOR flash memory device having multi-level memory cells, and a method of sensing the logic state of the multi-level memory cells. Background technique [0002] NOR flash memory is a popular form of non-volatile data storage used in various portable electronic devices such as cellular phones, personal digital assistants (PDAs), removable memory cards, and the like. The NOR flash memory is especially suitable for applications requiring high data access speed. For example, NOR flash memory is commonly used to store program code. In contrast, NAND flash memory is generally used for mass data storage due to its relatively low data access speed and its cheap price. [0003] A flash memory cell includes: a source and a drain, both of which are doped with N+-type impurities; and a channel formed in a P-type semicondu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/02G11C16/06G11C11/34G11C7/00H01L27/115H01L21/8247H10B69/00
CPCG11C5/147G11C7/06G11C11/5642G11C16/26G11C16/30
Inventor 金大汉李升根
Owner SAMSUNG ELECTRONICS CO LTD