Reference voltage generator for use in display applications

Abstract

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S / H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S / H circuit in a second group of N S / H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S / H circuits in the first group and a second input connected to an output of a corresponding one of the S / H circuits in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

Description

[0001] priority claim [0002] This application claims priority from the following patent applications: U.S. Patent Application No. 11 / 344,899 filed February 1, 2006 by Chor Yin Chia; , US Patent Application No. 11 / 204,480; US Provisional Patent Application No. 11 / 344,899 filed by Chor Yin Chia on February 25, 2005. technical field [0003] Embodiments of the present invention relate to the field of integrated circuits, and more particularly to voltage generators useful in display (eg, LCD) applications. Background technique [0004] In conventional flat panel display systems, such as liquid crystal display (LCD) systems, the brightness of individual pixels or elements is controlled by transistors. Active matrix displays include a type of dot matrix of transistors (eg, thin film transistors) arranged in rows and columns. Column lines are coupled to the drains or sources associated with each transistor in each column. Row lines are coupled to respective gates associated wi...

AI Technical Summary

Problems solved by technology

To handle this switching rate, use the figure 2 The architecture shown would require relatively large transistors (which are relatively expensive) and high currents, making them impractical for LCD applications where cost and size are critical

Also, for the same digital code, the output voltage may have large offsets due to mismatches in the multiple DACs 220 and output buffers 230

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