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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of deformation of semiconductor elements 3, difficulty in structural design, and low connection height of connecting terminals 4, so as to suppress deformation of connecting parts, improve structural design freedom, and reduce connection stress Effect

Inactive Publication Date: 2006-09-06
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, the connection height of the connection terminal 4 is low, and the semiconductor element 3 is deformed, so the possibility that the semiconductor element 3 is in contact with the substrate 1 is high.
[0006] Therefore, from the perspective of increasing the number of pins and reducing the pitch, it is difficult to design a structure that can cope with the increase in the connection load required for electrical connection due to the increase in the number of connection parts, and there is a problem that the degree of freedom in the design of the semiconductor device structure is reduced.

Method used

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  • Semiconductor device
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Examples

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Effect test

Embodiment approach 1

[0028] figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1 of the present invention.

[0029] Such as figure 1 As shown, a wiring circuit 11 including a connection electrode 5 and a resist 8 are disposed on one main surface of a substrate 1 . The resist may cover the wiring circuit 11 other than the connection electrode 5 or may expose the wiring circuit 11 . It is preferable to form the resist 8 on the wiring circuit 11 with such a thickness that there is no fear of pinholes in the resist 8, specifically 10 μm. A semiconductor element 3 having connection terminals 4 is mounted face down on the substrate 1 . The installation method is carried out by the following assembly method. That is, the semiconductor element 3 having the connection terminals 4 connected to the pads on the semiconductor element 3 is faced downward by a wire bonding device, and while heating, the substrate 1 is pressed with a pressure of 2...

Embodiment approach 2

[0038] figure 2 It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2 of the present invention.

[0039] The second embodiment has a structure in which the reinforcement via 7 extends to the lower surface of the connection electrode 4 and does not reach the other main surface side of the substrate 1 in the semiconductor device of the first embodiment.

[0040] Such as figure 2 As shown, a wiring circuit 11 including a connection electrode 5 and a resist 8 are disposed on one main surface of a substrate 1 . The resist may cover the wiring circuit 11 other than the connection electrode 5 or may expose the wiring circuit 11 . It is preferable to form the resist 8 on the wiring circuit 11 with such a thickness that there is no fear of pinholes in the resist 8, specifically 10 μm. A semiconductor element 3 having connection terminals 4 is mounted face down on the substrate 1 . The installation method is the following assembly...

Embodiment approach 3

[0050] image 3 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3 of the present invention.

[0051] This third embodiment has a structure in which the reinforcing via 7 is extended to the other main surface of the substrate 1 in the above-described first embodiment, and the reinforcing via 7 is electrically insulated from the connection electrode 5 .

[0052] Such as image 3 As shown, a wiring circuit 11 including a connection electrode 5 and a resist 8 are disposed on one main surface of a substrate 1 . The resist may cover the wiring circuit 11 other than the connection electrode 5 or may expose the wiring circuit 11 . It is preferable to form the resist 8 on the wiring circuit 11 with such a thickness that there is no fear of pinholes in the resist 8, specifically 10 μm. A semiconductor element 3 having connection terminals 4 is mounted face down on the substrate 1 . The installation method is carried out by the foll...

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PUM

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Abstract

According to the present invention, one or more reinforcing vias ( 7 ) or reinforcing metal layers are disposed on the inner side of connecting electrodes ( 5 ). With this configuration, strength increases relative to a load applied for mounting a semiconductor element ( 3 ) and the sinking of the connecting electrodes ( 5 ) is reduced. Thus, it is possible to reduce the connecting stress of the semiconductor device, reduce the deformation of a joint, and increase flexibility in process design.

Description

technical field [0001] The present invention relates to a semiconductor device which protects the integrated circuit part of an LSI chip, ensures stable electrical connection between external devices and the LSI chip, and is capable of high-density mounting, and particularly relates to a semiconductor device mounting a semiconductor element with many connection terminals. Background technique [0002] In recent years, information and communication equipment, business electronic equipment, household electronic equipment, measuring equipment, assembly robots and other industrial electronic equipment, medical electronic equipment, electronic toys and other fields have developed small and light weight, and there is a strong demand for semiconductor devices to be reduced. Small installation area. As one semiconductor device satisfying these requirements, a BGA (Ball Grid Array) or the like is used. On the other hand, as the density of semiconductor elements mounted on BGAs incre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/12
CPCH01L23/562H01L24/29H01L2224/81801H01L24/32H01L2224/1319H01L2224/83385H01L2224/32225H01L2224/13144H01L2224/16H01L2924/0105H01L2224/32057H01L2224/81191H01L2924/00013H01L2224/16225H01L2924/3511H01L2924/01006H01L2924/01079H01L2924/14H01L2924/15311H01L2224/83102H01L2924/15151H01L2224/83192H01L2224/73204H01L2224/92125H01L2224/13147H01L21/563H01L2224/131H01L2224/1134H01L2924/014H01L2224/81203H01L2924/01029H01L23/49822H01L2224/16238H01L23/3128H01L2924/01033H01L24/81H01L23/49827H01L2924/00011H01L2924/00014H01L2924/181H01L2224/13099H01L2924/00H01L2224/0401E06B9/362E06B9/386E06B9/388
Inventor 大隅贵寿阪下靖之
Owner PANASONIC CORP
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