Flat-face saliant-point type packing base-board for integrated circuit or discrete device

A planar bump type, discrete device technology, applied in the direction of electrical solid devices, semiconductor/solid device manufacturing, circuits, etc., can solve the problem that it is difficult to adapt to the development direction of thin and short packaging products, the overall weight of the chip package increases, and the technical requirements are getting higher and higher. Solve high-level problems to achieve the effect of facilitating technical control, reducing technical harshness, and reducing risks

Inactive Publication Date: 2006-10-25
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 3. Packaging cost: As the chip design becomes more and more complex, the chip size specifications are also more and more diversified, and ultra-long and ultra-wide chips continue to appear. Complete leadframe redesign at high cost
[0006] 4. Technical requirements: As the size of the base island continues to increase, the technical requirements for st

Method used

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  • Flat-face saliant-point type packing base-board for integrated circuit or discrete device
  • Flat-face saliant-point type packing base-board for integrated circuit or discrete device
  • Flat-face saliant-point type packing base-board for integrated circuit or discrete device

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0030] Example 1:

[0031] Structure of Example 1 Figure 7(a), Figure 7(a) is an integrated circuit or discrete device plane bump package substrate, the base island 1 and the lead 2 on the package substrate are distributed in the shape of bumps on the front surface of the substrate , there is a thin metal layer 3 connection between the bump and the bump, the base island 1 is a unit base island composed of multiple bumps, the pin 2 is a single bump, and the fronts of the base island 1 and the pin 2 are provided with The metal layer 4, the metal layer 4 is gold, or silver, or copper, or tin, or nickel, or nickel-palladium, and the metal layer can be a single layer or a multi-layer, and the metal layer 4 can be provided on the part of the convex in the unit base island on point or on all bumps. In a single integrated circuit or discrete device package formed during subsequent packaging, the number of base islands 1 can be one or more, that is, a single unit base island or multip...

Example Embodiment

[0040] Example 2:

[0041] The structure of Embodiment 2 is shown in FIG. 7( b ). On the basis of Embodiment 1, a metal layer 4 is provided on the backside of both the base island 1 and the lead 2 .

[0042] Its production method includes the following steps:

[0043] Step 1, with embodiment 1,

[0044] Step 2, with embodiment 1,

[0045] Step 3: Remove part of the mask on the front and back sides of the metal substrate 1 to expose the area on the metal substrate to be plated with a metal layer, such as image 3 (b),

[0046] Step 4. The method is the same as in Example 1, and the figure is shown in the figure Figure 4 (b),

[0047] Step 5, the method is the same as that of embodiment 1, and the figure sees Figure 5 (b),

[0048] Step 6, the method is the same as that of embodiment 1, the figure sees Image 6 (b),

[0049] Step 7. The method is the same as that of Example 1, and the diagram is shown in Figure 7(b).

Example Embodiment

[0050] Example 3:

[0051] The structure of Example 3 is shown in Figure 7(c), which is on the basis of Example 1, and the active material layer 5 is first provided on the front of both the base island 1 and the pin 2, and then the front of the active material layer 5 is provided. A metal layer 4 is provided. The activating substance 5 is nickel, or palladium, or nickel-palladium.

[0052] Its production method includes the following steps:

[0053] Step 1, with embodiment 1,

[0054] Step 2, with embodiment 1,

[0055] Step 3, with embodiment 1,

[0056] Step 4: Plate the area where the mask layer is removed in the previous process first with an activation material layer 5 such as Figure 4 (c), and then plated with metal layer 4, such as Figure 4 (e),

[0057] Step 5, the method is the same as that of embodiment 1, and the figure sees Figure 5 (c),

[0058] Step 6, the method is the same as that of embodiment 1, the figure sees Image 6 (c),

[0059] Step 7. The m...

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Abstract

This invention relates to a plane button package base plate of an IC or a discrete device and its processing method characterizing that base islands and pins are distributed on the front of the base plate in buttons connected by metal thin layers, the base island is the one composed of multiple buttons, the pin is single, the fronts of the islands and the pins have metal layers, the number of the islands is one or many in the package unit of a single IC or discrete device formed in the post package, namely, single unit island or multiple unit base islands composed of multiple buttons, the pins are arrayed at one side, both sides or three sides or surrounding the base islands.

Description

Technical field: [0001] The invention relates to a planar bump package substrate for an integrated circuit or a discrete device and a manufacturing method thereof. It belongs to the technical field of electronic components. Background technique: [0002] In the existing integrated circuit or discrete device planar bump package substrate, the base island on it is in the shape of a whole piece of metal. It mainly has the following deficiencies: [0003] 1. Packaging structure: Chip base islands correspond one-to-one, and the size of the base island must be larger than the chip size, which has great limitations and is difficult to adapt to chips of different sizes and specifications. [0004] 2. Packaging reliability: Since the chip is installed on the base island, the requirements for the material, flatness, surface quality, and cleanliness of the base island are extremely high; at the same time, because the entire metal base island is prone to large deformation stress after...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L21/48H01L21/60H01L23/12
CPCH01L2924/0002
Inventor 梁志忠王新潮于燮康陶玉娟
Owner JCET GROUP CO LTD
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