Semiconductor storage device and method for manufacturing same

Abstract

A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1 a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1 a; a first well 1 b that is formed on the surface of the substrate 1 below the selector gate 3 ; a floating gate 6 that is located via an insulating film 8 a on the surface of the bottom section and sidewall section of the trench section 1 a; a second well 1 c that is formed on the surface of the bottom section of the trench section 1 a below the floating gate 6 ; a first diffusion area 7 a that is formed on the surface of the bottom section of the trench section 1 a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6 ; and where the area near the sidewall surface and bottom surface of the trench section 1 a forms a channel in the selector gate 3 ; and the impurity density of the first well 1 b is not more than the impurity density of the second well 1 c.

Description

technical field [0001] The present invention relates to a semiconductor memory device having cell transistors and a manufacturing method thereof, and more particularly to a semiconductor memory device storing multi-bit information per cell and a manufacturing method thereof. Background technique [0002] Among conventional semiconductor storage devices, known nonvolatile semiconductor storage devices that store multi-bit information per cell Figure 14 A nonvolatile semiconductor memory device having a cell transistor is shown (conventional example 1). In the nonvolatile semiconductor memory device according to Conventional Example 1, there are two strip-shaped opposite conductivity type regions 123a, 123b formed on the surface layer of a semiconductor substrate 121 sandwiching a strip-shaped semiconductor layer 124a of one conductivity type. from one side of the opposite conductivity type region 123a to one side of the semiconductor layer 124a, the first floating gate 127a ...

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Problems solved by technology

That is, in order to suppress punch-through, it is necessary to increase the impurity concentration of the well 201b of the substrate 201 under the floating gate 206 (the region between the inversion layer 220 and the second diffusion region 207b), but in this case, the selection gate transistor A trade-off between increased threshold voltage and decreased current during readout

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